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    Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
    1.
    发明授权
    Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same 有权
    用于执行DRAM刷新操作的存储器电路，系统和模块及其操作方法

    公开(公告)号：US08588017B2

    公开(公告)日：2013-11-19

    申请号：US13236972

    申请日：2011-09-20

    申请人： Chul-woo Park ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

    发明人： Chul-woo Park ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

    IPC分类号： G11C29/00

    CPC分类号： G11C29/808 ,  G06F2213/0038 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C2211/4062

    摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

    摘要翻译： 存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作 命令。

    Memory device for managing timing parameters
    5.
    发明授权
    Memory device for managing timing parameters 有权
    用于管理时序参数的存储器

    公开(公告)号：US08693269B2

    公开(公告)日：2014-04-08

    申请号：US13569636

    申请日：2012-08-08

    申请人： Uk-song Kang ,  Chul-woo Park ,  Hak-soo Yu ,  Hong-sun Hwang

    发明人： Uk-song Kang ,  Chul-woo Park ,  Hak-soo Yu ,  Hong-sun Hwang

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4076 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/4093

    摘要： A method of performing write operations in a memory device including a plurality of bank is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.

    摘要翻译： 执行在包括多个存储体的存储器件中执行写入操作的方法。 每个银行包括至少包括第一子银行和第二子银行的两个或多个子行。 该方法包括：执行第一行周期以写入第一子行的第一字线，第一行周期包括多个第一子周期，用于执行特定动作的每个子周期; 以及执行第二行周期以写入所述第二子行的第一字线，所述第二行周期包括与所述多个第一子周期相同类型的多个第二子周期。 第一行周期与第二行周期重叠，第一子周期的第一类型子周期与第二子周期的第二类型子周期重叠，第一类型和第二类型是不同类型。

    Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same
    6.
    发明授权
    Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same 有权
    具有堆叠结构的半导体存储器件，包括基于电阻开关的逻辑电路及其制造方法

    公开(公告)号：US08553445B2

    公开(公告)日：2013-10-08

    申请号：US13224410

    申请日：2011-09-02

    申请人： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

    发明人： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

    IPC分类号： G11C11/00

    CPC分类号： H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

    摘要： Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

    摘要翻译： 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

    Semiconductor memory devices and semiconductor memory systems
    9.
    发明授权
    Semiconductor memory devices and semiconductor memory systems 有权
    半导体存储器件和半导体存储器系统

    公开(公告)号：US08705297B2

    公开(公告)日：2014-04-22

    申请号：US13282830

    申请日：2011-10-27

    申请人： Sua Kim ,  Chul-woo Park ,  Hong-sun Hwang ,  Hak-soo Yu

    发明人： Sua Kim ,  Chul-woo Park ,  Hong-sun Hwang ,  Hak-soo Yu

    IPC分类号： G11C7/00

    CPC分类号： G11C7/18 ,  G11C7/06 ,  G11C2207/002 ,  G11C2207/005

    摘要： A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal.

    摘要翻译： 半导体存储器件包括至少一个存储单元块和至少一个连接单元。 所述至少一个存储单元块具有包括连接到第一位线的至少一个第一存储单元的第一区域和包括连接到第二位线的至少一个第二存储器单元的第二区域。 所述至少一个连接单元被配置为基于第一控制信号选择性地将第一位线连接到对应的位线读出放大器，并且被配置为经由对应的全局位选择性地将第二位线连接到对应的位线读出放大器 基于第二控制信号。

    Memory device capable of quickly repairing fail cell
    10.
    发明授权
    Memory device capable of quickly repairing fail cell 有权

    公开(公告)号：US10235258B2

    公开(公告)日：2019-03-19

    申请号：US14683705

    申请日：2015-04-10

    申请人： Jong-pil Son ,  Chul-woo Park ,  Su-a Kim

    发明人： Jong-pil Son ,  Chul-woo Park ,  Su-a Kim

    IPC分类号： G06F11/20 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G06F11/10 ,  G11C29/04

    摘要： The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.