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    Electronic fuse structure and method of manufacturing
    1.
    发明授权
    Electronic fuse structure and method of manufacturing 有权
    电子熔断器结构及制造方法

    公开(公告)号：US06633055B2

    公开(公告)日：2003-10-14

    申请号：US09303509

    申请日：1999-04-30

    申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Max G. Levy ,  Timothy D. Sullivan ,  William R. Tonti

    发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Max G. Levy ,  Timothy D. Sullivan ,  William R. Tonti

    IPC分类号： H01L2974

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A gap conductor structure for an integrated electronic circuit that may function as an electronic fuse device or as a low capacitance inter level signal line is integrated as part of the semi-conductor chip wiring. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to melt a part of the conducting line. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer. Furthermore, conducting structures completely or partially exposed in the air gap may function as low capacitance minimum delay transmission lines.

    摘要翻译： 作为半导体芯片布线的一部分，集成电子电路的可用作电子熔断器件或低电容级间信号线的间隙导体结构被集成。 间隙导电结构包括一个或多个预定体积的气隙区域，其完全或部分地暴露IC中的层间导体层的长度。 或者，气隙区域可以完全位于相应导体下方的电介质区域内并被绝缘体分隔开。 当用作熔丝时，间隙区域用于降低远离导体的暴露部分的热导率，使得能够以较低的施加电压在导线中产生更高的热流，从而熔化导电线的一部分。 间隙的存在以及保险丝的存在是可扩展的，并且可以根据电路设计者定义的保险丝的特性来适应其必须携带的电流的容量。 此外，在气隙中完全或部分暴露的导电结构可用作低电容最小延迟传输线

    Electrically programmable antifuses and methods for forming the same
    3.
    发明授权
    Electrically programmable antifuses and methods for forming the same 有权
    电子可编程反熔丝及其形成方法

    公开(公告)号：US06388305B1

    公开(公告)日：2002-05-14

    申请号：US09466495

    申请日：1999-12-17

    申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

    发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

    IPC分类号： H01L2900

    CPC分类号： H01L21/763 ,  H01L23/5252 ,  H01L27/10861 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench. The second logic element is configured so that a predetermined voltage or higher applied between the electrode and the first layer causes a breakdown near the merge location.

    摘要翻译： 首先，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该第一导电类型的半导体衬底包括在衬底的表面下面的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。 沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。 第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。 第二次，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该半导体衬底包括形成在衬底的表面中的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。 沟槽包括内表面，衬在内表面的第一电介质材料和填充衬里沟槽的第二电介质材料。 第二逻辑元件还包括形成在第一层的一部分上并且在合并位置处接触衬套在沟槽上的第一介电材料的电介质层; 以及在电介质层和填充沟槽的一部分上延伸的电极。 第二逻辑元件被配置为使得施加在电极和第一层之间的预定电压或更高的电压导致合并位置附近的击穿。

    Method and apparatus for semiconductor integrated circuit testing and burn-in
    4.
    发明授权
    Method and apparatus for semiconductor integrated circuit testing and burn-in 失效
    用于半导体集成电路测试和老化的方法和装置

    公开(公告)号：US06574763B1

    公开(公告)日：2003-06-03

    申请号：US09473886

    申请日：1999-12-28

    申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： G01R3128

    CPC分类号： G01R31/287

    摘要： A burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-in process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ, and lowering the temperature of the memory array to ambient temperature to complete the burn-in process. An apparatus for carrying out the above process is provided that includes a test circuit for generating a test pattern and for applying the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response and an expected response of the memory array to the test pattern and detects faulty and operable bits based thereon. A failed address buffer register, coupled to the comparison circuit and to the test circuit, stores an address of each addressable storage location that has a faulty bit. Sparing control logic, coupled to the failed address buffer register and adapted to couple to the memory array, reads out each address stored by the failed address buffer register and replaces each faulty bit with a redundant operable bit.

    摘要翻译： 为具有冗余位和可寻址存储位置的存储器阵列提供老化过程。 老化过程包括以下步骤：将存储器阵列的温度升高到预定温度，测试阵列中的所有位，检测故障位和可操作位，用冗余的可操作位代替故障位，校正在 阵列原位，并将存储器阵列的温度降低到环境温度以完成老化过程。 提供了一种用于执行上述处理的装置，其包括用于生成测试图案并将测试图案应用于存储器阵列的测试电路，以便测试存储器阵列内的所有位。 耦合到测试电路并且适于耦合到存储器阵列的比较电路将存储器阵列的实际响应和预期响应与测试模式进行比较，并基于此检测故障和可操作的位。 耦合到比较电路和测试电路的故障地址缓冲寄存器存储具有错误位的每个可寻址存储位置的地址。 冗余控制逻辑耦合到故障地址缓冲寄存器并适于耦合到存储器阵列，读出由故障地址缓冲寄存器存储的每个地址，并用冗余可操作位替换每个故障位。

    Structures for wafer level test and burn-in
    5.
    发明授权
    Structures for wafer level test and burn-in 失效
    晶圆级测试和老化的结构

    公开(公告)号：US06233184B1

    公开(公告)日：2001-05-15

    申请号：US09191954

    申请日：1998-11-13

    申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    IPC分类号： G11C2900

    CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

    摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

    摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

    High frequency valid data strobe
    6.
    发明授权
    High frequency valid data strobe 失效
    高频有效数据选通

    公开(公告)号：US06177807B1

    公开(公告)日：2001-01-23

    申请号：US09322465

    申请日：1999-05-28

    申请人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    发明人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： G03K1716

    CPC分类号： G06F13/4086 ,  H03K5/06 ,  H04L25/0298

    摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.

    摘要翻译： 具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。 数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。 具有递增可变长度的传输线短截线连接到控制线14的存储器控​​制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路 在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。

    Structures for wafer level test and burn-in
    7.
    发明授权
    Structures for wafer level test and burn-in 失效
    晶圆级测试和老化的结构

    公开(公告)号：US06426904B2

    公开(公告)日：2002-07-30

    申请号：US09803500

    申请日：2001-03-09

    申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    IPC分类号： G11C2900

    CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

    摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

    摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

    Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application
    9.
    发明授权
    Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application 失效
    硅抗熔丝结构，绝缘体上的体和硅绝缘体制造方法和应用

    公开(公告)号：US06396120B1

    公开(公告)日：2002-05-28

    申请号：US09527191

    申请日：2000-03-17

    申请人： Claude L Bertin ,  Toshiharu Furukawa ,  Erik L. Hedberg ,  Jack A. Mandelman ,  William R. Tonti ,  Richard Q. Williams

    发明人： Claude L Bertin ,  Toshiharu Furukawa ,  Erik L. Hedberg ,  Jack A. Mandelman ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L2972

    CPC分类号： H01L29/78696 ,  H01L21/823412 ,  H01L21/823456 ,  H01L23/5252 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate. In a second embodiment, the semiconductor device comprises a substrate having a trough formed in a top surface of the substrate, a relatively thick insulator layer over the top surface of the substrate, a relatively thin insulator layer over the trough that is breached by a breakdown voltage applied to the trough, a region comprised of a material on the relatively thin insulator layer over the trough for becoming electrically coupled to the substrate after the relatively thin insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to said substrate.

    摘要翻译： 一种使用场强增强区域的方法和半导体结构，其中氧化物厚度大大降低，从而允许在不损坏标准CMOS逻辑的老化电压下进行反熔丝编程。 半导体器件包括具有突出的突起终止于基本尖锐点的衬底，凸起突起上的绝缘体层足够薄以致被施加到尖锐点的击穿电压所破坏，由绝缘体上的材料构成的区域 在绝缘体层被击穿电压破坏之后用于电耦合到衬底的凸起突起，以及用于向衬底提供击穿电压的触点。 在第二实施例中，半导体器件包括在衬底的顶表面中形成有槽的衬底，在衬底的顶表面上方的相对较厚的绝缘体层，在槽的相对较薄的绝缘体层，其被破坏 电压施加到槽，由比较薄的绝缘体层上的材料组成的区域，该沟槽在相对较薄的绝缘体层被击穿电压破坏之后用于变成与电极耦合的衬底;以及用于将击穿电压提供给 所述基板。

    Integrated memory cube structure
    10.
    发明授权
    Integrated memory cube structure 失效
    集成内存立方体结构

    公开(公告)号：US5561622A

    公开(公告)日：1996-10-01

    申请号：US120993

    申请日：1993-09-13

    申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

    发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

    IPC分类号： G11C5/00 ,  H01L25/065 ,  G11C5/06 ,  H01L23/02

    CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/10253

    摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

    摘要翻译： 一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。