公开(公告)号：US5625233A

公开(公告)日：1997-04-29

申请号：US372633

申请日：1995-01-13

申请人： Cyril Cabral, Jr. ,  Evan G. Colgan ,  Alfred Grill

发明人： Cyril Cabral, Jr. ,  Evan G. Colgan ,  Alfred Grill

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/532 ,  H01L27/108 ,  H01L23/482 ,  H01L29/45

CPC分类号： H01L21/76858 ,  H01L21/76841 ,  H01L23/53223 ,  H01L28/60 ,  H01L28/75 ,  H01L28/55 ,  H01L2924/0002

摘要： The use of a bi-layer thin film structure consisting of aluminum or aluminide on a refractory metal layer as a diffusion barrier to oxygen penetration at high temperatures for preventing the electrical and mechanical degradation of the refractory metal for use in applications such as a capacitor electrode for high dielectric constant materials.

摘要翻译： 在难熔金属层上使用由铝或铝化物组成的双层薄膜结构作为高温氧渗透的扩散阻挡层，用于防止难熔金属在诸如电容器电极之类的应用中的电和机械降解 用于高介电常数材料。

公开(公告)号：US08954712B2

公开(公告)日：2015-02-10

申请号：US13313145

申请日：2011-12-07

申请人： Evan G. Colgan ,  Monty M. Denneau ,  Daniel M. Kuchta

发明人： Evan G. Colgan ,  Monty M. Denneau ,  Daniel M. Kuchta

IPC分类号： G06F15/163 ,  G06F15/173

CPC分类号： H04B10/40 ,  G06F15/161 ,  G06F15/163 ,  G06F15/173 ,  G06F15/17337 ,  H04B10/2503 ,  H04L5/14

摘要： Node Interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link.

摘要翻译： 提供节点互连架构来实现高性能超级计算机。 例如，用于连接超级计算机的多个节点（或处理器）的节点互连体系架构是使用提供超级计算机的任何两个处理器之间的两个独立通信路径的全对电连接网络来实现的，其中a 通信路径最多包括两个电连接和一个光链路。

公开(公告)号：US08693200B2

公开(公告)日：2014-04-08

申请号：US13368031

申请日：2012-02-07

申请人： Evan G. Colgan ,  Michael A. Gaynes ,  Jeffrey A. Zitz

发明人： Evan G. Colgan ,  Michael A. Gaynes ,  Jeffrey A. Zitz

IPC分类号： H05K7/20

CPC分类号： H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

摘要： A cooling module for cooling a semiconductor is provided and includes a land grid array (LGA) interposer, a substrate with an LGA side and a chip side, a cooler, a load frame attached to the substrate and formed to define an aperture in which the cooler is removably disposable, a spring clamp removably attachable to the load frame and configured to apply force from the load frame to the cooler such that the substrate and the cooler are urged together about the semiconductor and a load assembly device configured to urge the load frame and the LGA interposer together.

摘要翻译： 提供了一种用于冷却半导体的冷却模块，其包括平台栅格阵列（LGA）插入器，具有LGA侧和芯片侧的衬底，冷却器，附接到衬底并形成以限定孔径的负载框架 冷却器可拆卸地是一次性的，弹簧夹可移除地附接到负载框架并且构造成将力从负载框架施加到冷却器，使得衬底和冷却器围绕半导体被一起被推动在一起;以及负载组件装置，其构造成推动负载框架 和LGA插入器在一起。

公开(公告)号：US08569874B2

公开(公告)日：2013-10-29

申请号：US13043749

申请日：2011-03-09

申请人： Evan G. Colgan ,  Monty M. Denneau ,  Sampath Purushothaman ,  Klmberley A. Kelly ,  Roy R. Yu

发明人： Evan G. Colgan ,  Monty M. Denneau ,  Sampath Purushothaman ,  Klmberley A. Kelly ,  Roy R. Yu

IPC分类号： H01L23/66 ,  H01L23/64

CPC分类号： G11C5/025 ,  G11C5/063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip.

摘要翻译： 芯片堆叠结构包括具有有源器件表面的逻辑芯片和垂直对齐的存储器单元的存储器片，使得存储器片的表面垂直于逻辑芯片的有源器件表面定向。 芯片堆叠结构还包括在存储器片的上表面上图案化的布线，布线将存储器片的存储器引线电连接到对应于逻辑芯片的逻辑电路连接的逻辑栅极。

公开(公告)号：US20130091886A1

公开(公告)日：2013-04-18

申请号：US13271290

申请日：2011-10-12

申请人： Levi A. CAMPBELL ,  Richard C. CHU ,  Evan G. Colgan ,  Milnes P. DAVID ,  Michael J. ELLSWORTH, JR. ,  Madhusudan K. IYENGAR ,  Robert E. SIMONS

发明人： Levi A. CAMPBELL ,  Richard C. CHU ,  Evan G. Colgan ,  Milnes P. DAVID ,  Michael J. ELLSWORTH, JR. ,  Madhusudan K. IYENGAR ,  Robert E. SIMONS

IPC分类号： F25B43/00 ,  F25D31/00 ,  B23P15/26

CPC分类号： F25B43/003 ,  F25B2400/01 ,  H05K7/20327 ,  H05K7/20809

摘要： Apparatuses and methods are provided for facilitating cooling of an electronic component. The apparatus includes a vapor-compression refrigeration system. The vapor-compression refrigeration system includes an expansion component, an evaporator, a compressor, and a condenser coupled in fluid communication via a refrigerant flow path. The evaporator is coupled to and cools the electronic component. The apparatus further includes a contaminant extractor coupled in fluid communication with the refrigerant flow path. The extractor includes a refrigerant boiling filter and a heater. At least a portion of refrigerant passing through the refrigerant flow path passes through the refrigerant boiling filter, and the heater provides heat to the refrigerant boiling filter to boil refrigerant passing through the filter. By boiling refrigerant passing through the filter, contaminants are extracted from the refrigerant, and are deposited in the refrigerant boiling filter.

摘要翻译： 提供了便于冷却电子部件的装置和方法。 该装置包括蒸气压缩制冷系统。 蒸汽压缩式制冷系统包括膨胀部件，蒸发器，压缩机以及通过制冷剂流动路径流体连通的冷凝器。 蒸发器与电子部件联接并冷却。 该装置还包括与制冷剂流动路径流体连通地联接的污染物提取器。 提取器包括制冷剂沸腾过滤器和加热器。 通过制冷剂流路的制冷剂的至少一部分通过制冷剂沸腾过滤器，并且加热器向制冷剂沸腾过滤器提供热量以沸腾通过过滤器的制冷剂。 通过沸腾通过过滤器的制冷剂，污染物从制冷剂中排出，并沉积在制冷剂沸腾过滤器中。

公开(公告)号：US08330262B2

公开(公告)日：2012-12-11

申请号：US12698529

申请日：2010-02-02

申请人： Evan G. Colgan ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Evan G. Colgan ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H01L23/02

CPC分类号： H01L23/49816 ,  B23P11/00 ,  H01L21/78 ,  H01L2924/0002 ,  H05K1/11 ,  H05K1/14 ,  H05K7/00 ,  Y10T29/49826 ,  H01L2924/00

摘要： An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

摘要翻译： 增强的3D集成结构包括结合到垂直堆叠的存储器片的集合的逻辑微处理器芯片和包括光电子器件的可选的一组外部垂直片。 这样一种装置使得能够靠近逻辑电路的高存储器内容和用于逻辑到存储器通信的高带宽。 此外，在垂直切片堆叠的外切片中提供光电子器件可实现彼此相邻或相邻封装衬底上安装的相邻增强3D模块之间的逻辑处理器芯片之间的高带宽直接通信。 制造这种结构的方法包括使用能够对垂直切片堆叠进行晶片格式处理的模板组件。

公开(公告)号：US08171630B2

公开(公告)日：2012-05-08

申请号：US12047603

申请日：2008-03-13

申请人： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

发明人： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC分类号： H01R43/16

CPC分类号： H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

摘要： A method of producing a land grid array (LGA) interposer structure includes mounting at least one interposer on a first surface of an electrically insulating carrier plane. The interposer selectively having a hemi-toroidal, conical, dome-shaped conic section, generally cylindrical or hemi-spherical configuration in transverse cross-section and being constituted of a dielectric elastomeric material. The method includes positioning a plurality of electrically-conductive elements about the surface of the hemi-toroidal interposer that extend radially inwardly and downwardly from an uppermost end thereof. The method further includes mounting said at least one component comprising at least one hemi-toroidal interposer mounted on said opposite side of said carrier plane. Additionally the method includes forming at least one through-extending via in said electrically-insulating carrier plane, and forming electrical connections between said first-mentioned at least one hemi-toroidal interposer and said further at least one inverted hemi-toroidal interposer.

摘要翻译： 一种制造焊盘格栅阵列（LGA）插入器结构的方法包括在电绝缘载体平面的第一表面上安装至少一个插入件。 中间层选择性地具有半环形，圆锥形的圆顶形圆锥形截面，横截面为大致圆柱形或半球形，并由介电弹性体材料构成。 该方法包括围绕半环形插入器的表面定位多个导电元件，其从其最上端径向向内和向下延伸。 该方法还包括安装所述至少一个部件，该部件包括安装在所述载体平面的相对侧上的至少一个半环形插入器。 另外，该方法包括在所述电绝缘载体平面中形成至少一个贯通孔，以及在所述第一提到的至少一个半环形插入件与所述另外的至少一个反向半环形插入件之间形成电连接。

公开(公告)号：US20110188209A1

公开(公告)日：2011-08-04

申请号：US12698529

申请日：2010-02-02

申请人： Evan G. Colgan ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Evan G. Colgan ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H05K7/00 ,  H05K1/14 ,  H05K1/11 ,  B23P11/00

CPC分类号： H01L23/49816 ,  B23P11/00 ,  H01L21/78 ,  H01L2924/0002 ,  H05K1/11 ,  H05K1/14 ,  H05K7/00 ,  Y10T29/49826 ,  H01L2924/00

摘要： An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

摘要翻译： 增强的3D集成结构包括结合到垂直堆叠的存储器片的集合的逻辑微处理器芯片和包括光电子器件的可选的一组外部垂直片。 这样一种装置使得能够靠近逻辑电路的高存储器内容和用于逻辑到存储器通信的高带宽。 此外，在垂直切片堆叠的外切片中提供光电子器件可实现彼此相邻或相邻封装衬底上安装的相邻增强型3D模块之间的逻辑处理器芯片之间的高带宽直接通信。 制造这种结构的方法包括使用能够对垂直切片堆叠进行晶片格式处理的模板组件。

公开(公告)号：US20100279521A1

公开(公告)日：2010-11-04

申请号：US12061774

申请日：2008-04-03

申请人： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

发明人： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC分类号： H01R12/00

CPC分类号： H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

摘要翻译： 一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置，并且从其最上端向内和向下自由地延伸，与位于电绝缘载体平面相反侧的至少一个部件电接触 。

公开(公告)号：US07658616B2

公开(公告)日：2010-02-09

申请号：US12328026

申请日：2008-12-04

申请人： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

发明人： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC分类号： H01R12/00

CPC分类号： H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and interposer groupings of different height being mounted on a first surface of said carrier plane. Each interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of each hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

摘要翻译： 包括电绝缘载体平面和不同高度的插入物分组的平面栅格阵列（LGA）插入器结构安装在所述载体平面的第一表面上。 每个插入件在横截面中具有半环形结构并且由介电弹性体材料构成。 多个导电元件围绕每个半环形插入器的表面布置，并且从其最上端向内和向下自由地延伸，与位于电绝缘载体平面相反侧的至少一个部件电接触。