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    SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    2.
    发明申请
    SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权

    公开(公告)号：US20210384183A1

    公开(公告)日：2021-12-09

    申请号：US17286738

    申请日：2019-10-18

    Applicant: DAICEL CORPORATION

    Inventor： Naoko TSUJI

    IPC: H01L25/00 ,  H01L21/683 ,  H01L21/304 ,  H01L21/768 ,  H01L23/00 ,  H01L21/78 ,  C09J171/02 ,  C09J183/04 ,  C09J167/02 ,  C09J129/14

    Abstract: Provided is a technique suitable for multilayering thin semiconductor elements via adhesive bonding while avoiding wafer damage in a method of manufacturing a semiconductor device, the method in which semiconductor elements are multilayered through laminating wafers in which the semiconductor elements are fabricated. The method of the present invention includes bonding and removing. In the bonding step, a back surface 1b side of a thinned wafer 1T in a reinforced wafer 1R having a laminated structure including a supporting substrate S, a temporary adhesive layer 2, and the thinned wafer 1T is bonded via an adhesive to an element forming surface 3a of a wafer 3. A temporary adhesive for forming the temporary adhesive layer 2 contains a polyvalent vinyl ether compound, a compound having two or more hydroxy groups or carboxy groups and thus capable of forming a polymer with the polyvalent vinyl ether compound, and a thermoplastic resin. The adhesive contains a polymerizable group-containing polyorganosilsesquioxane. In the removing step, a temporary adhesion by the temporary adhesive layer 2 between the supporting substrate S and the thinned wafer 1T is released to remove the supporting substrate S.

    INSULATING FILM FORMING COMPOSITION, INSULATING FILM, AND SEMICONDUCTOR DEVICE PROVIDED WITH INSULATING FILM
    3.
    发明申请
    INSULATING FILM FORMING COMPOSITION, INSULATING FILM, AND SEMICONDUCTOR DEVICE PROVIDED WITH INSULATING FILM 有权

    公开(公告)号：US20210139652A1

    公开(公告)日：2021-05-13

    申请号：US16612001

    申请日：2018-04-26

    Applicant: DAICEL CORPORATION

    Inventor： Hiroto MIYAKE ,  Naoko TSUJI ,  Akira YAMAKAWA

    IPC: C08G77/42 ,  C09D183/06 ,  C08G77/14 ,  C08G59/32 ,  C08G59/38 ,  H01L23/29

    Abstract: The present invention provides an insulating film forming composition that excels in insulating properties and heat resistance, suppresses the occurrence of warpage, and can form an insulating film with excellent adhesion. The insulating film forming composition of the present invention contains, as a polymerizable compound, a polyorganosilsesquioxane containing siloxane constituent units; wherein the total content of: constituent units represented by formula (I) [RaSiO3/2] (I) and constituent units represented by formula (II) [RaSiO2/2(ORb)] (II) is greater than or equal to 55 mol % of the total amount of the siloxane constituent units; and the polyorganosilsesquioxane has a number average molecular weight of from 500 to 10000 and an epoxy equivalent of from 200 to 2000 g/eq.

    ADHESIVE AGENT COMPOSITION FOR MULTILAYER SEMICONDUCTOR
    4.
    发明申请
    ADHESIVE AGENT COMPOSITION FOR MULTILAYER SEMICONDUCTOR 审中-公开
    多层半导体的粘合剂组合物

    公开(公告)号：US20160215183A1

    公开(公告)日：2016-07-28

    申请号：US15025143

    申请日：2014-09-25

    Applicant: DAICEL CORPORATION

    Inventor： Hiroki TANAKA ,  Katsuhiro NAKAGUCHI ,  Kiyoharu TSUTSUMI ,  Yousuke ITO ,  Naoko TSUJI

    IPC: C09J163/00 ,  C09J7/02 ,  H01L23/00

    CPC classification number: C09J163/00 ,  C08G59/68 ,  C09J7/35 ,  C09J2203/326 ,  C09J2463/00 ,  H01L23/293 ,  H01L24/83 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/83855 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is an adhesive composition for multilayer semiconductors. The adhesive composition gives, when applied and dried by heating, an adhesive layer that has approximately no adhesiveness at a temperature lower than 50° C., but, when heated at such a temperature as to less cause damage to semiconductor chips, offers adhesiveness and is rapidly cured thereafter. This adhesive composition for multilayer semiconductors includes a polymerizable compound (A), at least one of a cationic-polymerization initiator (B1) and an anionic-polymerization initiator (B2), and a solvent (C). The polymerizable compound (A) contains 80% by weight or more of an epoxide having a softening point or melting point of 50° C. or higher. The cationic-polymerization initiator (B1) gives a composition having a thermal curing time of 3.5 minutes or longer at 130° C., where the composition contains 1 part by weight of the cationic-polymerization initiator (B1) and 100 parts by weight of 3,4-epoxycyclohexylmethyl (3,4-epoxy)cyclohexanecarboxylate. The anionic-polymerization initiator (B2) gives a composition having a thermal curing time of 3.5 minutes or longer at 130° C., where the composition contains 1 part by weight of the anionic-polymerization initiator (B2) and 100 parts by weight of bisphenol-A diglycidyl ether.

    Abstract translation: 提供了一种用于多层半导体的粘合剂组合物。 粘合剂组合物通过加热施加和干燥时，在低于50℃的温度下具有大致无粘合性的粘合剂层，但是当在较低温度下加热以致对半导体芯片造成损害时，提供粘合性和 此后迅速治愈。 该多层半导体用粘合剂组合物包含聚合性化合物（A），阳离子聚合引发剂（B1）和阴离子聚合引发剂（B2）中的至少一种和溶剂（C）。 可聚合化合物（A）含有80重量％以上的软化点或熔点为50℃以上的环氧化物。 阳离子聚合引发剂（B1）在130℃下得到热固化时间为3.5分钟以上的组合物，其中组合物含有1重量份的阳离子聚合引发剂（B1）和100重量份的 3,4-环氧环己基甲基（3,4-环氧）环己烷羧酸酯。 阴离子聚合引发剂（B2）在130℃下得到热固化时间为3.5分钟以上的组合物，其中组合物含有1重量份的阴离子聚合引发剂（B2）和100重量份的 双酚A二缩水甘油醚。

    ADHESIVE LAYER FORMING DEVICE, SEMICONDUCTOR CHIP PRODUCTION LINE, AND METHOD FOR PRODUCING LAMINATE
    5.
    发明申请
    ADHESIVE LAYER FORMING DEVICE, SEMICONDUCTOR CHIP PRODUCTION LINE, AND METHOD FOR PRODUCING LAMINATE 有权

    公开(公告)号：US20210134622A1

    公开(公告)日：2021-05-06

    申请号：US16612187

    申请日：2018-04-18

    Applicant: DAICEL CORPORATION

    Inventor： Yoshinori FUNAKI ,  Naoko TSUJI

    IPC: H01L21/67 ,  H01L21/683 ,  B32B37/12 ,  B32B9/00 ,  B32B7/12

    Abstract: Provide are: a method for producing a laminate having an adhesive layer on one surface of a semiconductor wafer, with the adhesive layer being less likely to foam during wafer bonding under reduced pressure, curing of an adhesive being less likely to occur, and also allowing a tact time to be shortened; and an adhesive layer forming device to be used in the method. The adhesive layer forming device for forming an adhesive layer by removing a solvent in a coating film coated and formed on one surface of a semiconductor wafer includes: a lower plate on which the semiconductor wafer is placed; an upper cover configured to form a closed space together with the lower plate, the closed space having a volume of 10 liters or less; and pressure reducing means for reducing pressure in the closed space.

    CURABLE COMPOSITION FOR ADHESIVE AGENTS, ADHESIVE SHEET, CURED ARTICLE, LAMINATE, AND DEVICE
    6.
    发明申请
    CURABLE COMPOSITION FOR ADHESIVE AGENTS, ADHESIVE SHEET, CURED ARTICLE, LAMINATE, AND DEVICE 审中-公开

    公开(公告)号：US20200148926A1

    公开(公告)日：2020-05-14

    申请号：US16614146

    申请日：2018-05-16

    Applicant: DAICEL CORPORATION

    Inventor： Akira YAMAKAWA ,  Naoko TSUJI

    IPC: C09J183/04 ,  C08G77/04 ,  B32B7/12 ,  C09J11/06 ,  C09J5/06

    Abstract: The present invention is to provide a curable composition for adhesive agents that cures at a low temperature and that can form a cured article having excellent heat resistance, crack resistance, and adhesive properties and tight bonding properties for adhereds. The present invention provides a curable composition for adhesive agents containing a polyorganosilsesquioxane (A) having a constituent unit represented by Formula (1) below; a mole ratio of a constituent unit represented by Formula (I) below to a constituent unit represented by Formula (II) below (constituent unit represented by Formula (I)/constituent unit represented by Formula (II)) being from 20 to 500; a proportion of the constituent unit represented by Formula (1) below and a constituent unit represented by Formula (4) below being from 55 to 100 mol % relative to a total amount (100 mol %) of siloxane constituent units; a number average molecular weight being from 2500 to 50000; and a molecular weight dispersity (weight average molecular weight/number average molecular weight) being from 1.0 to 4.0.

    SILANE COUPLING AGENT
    8.
    发明公开
    SILANE COUPLING AGENT 审中-公开

    公开(公告)号：US20230357285A1

    公开(公告)日：2023-11-09

    申请号：US18021942

    申请日：2021-08-05

    Applicant: DAICEL CORPORATION

    Inventor： Naoko TSUJI ,  Shinji MAETANI

    IPC: C07F7/08 ,  C09J183/06 ,  C09J11/06

    CPC classification number: C07F7/0836 ,  C09J11/06 ,  C09J183/06 ,  C09J2203/326 ,  C09J2483/00

    Abstract: Provided is a silane coupling agent with a low viscosity, excellent applicability, and excellent effect of improving adhesion between inorganic matter and organic matter. The silane coupling agent of the present disclosure contains a silicon compound below and water, having a concentration of the silicon compound of from 0.01 to 10 wt.%, the silicon compound: containing a compound (I) represented by Formula (1) and a polycondensate of the compound (I), wherein a ratio of contents of the compound (I) to a compound (II), [compound (I)/compound (II); weight ratio], the compound (II) being a polycondensate of the compound (I) and having a weight average molecular weight of from 200 to 10000 calibrated with a polystyrene standard, is from 1/99 to 95/5.

    SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    10.
    发明申请
    SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权

    公开(公告)号：US20210391165A1

    公开(公告)日：2021-12-16

    申请号：US17286725

    申请日：2019-10-18

    Applicant: DAICEL CORPORATION

    Inventor： Naoko TSUJI

    IPC: H01L21/02

    Abstract: An object of the present invention is to provide a technique suitable for achieving low wiring resistance and reducing a variation in the resistance value between semiconductor elements to be multilayered in a method of manufacturing a semiconductor device in which the semiconductor elements are multilayered through laminating semiconductor wafers via an adhesive layer. The method of the present invention includes first to third processes. In the first process, a wafer laminate Y is prepared, the wafer laminate Y having a laminated structure including a wafer 3, wafers 1T with a thickness from 1 to 20 um, and an adhesive layer 4 with a thickness from 0.5 to 4.5 μm interposed between a main surface 3a of the wafer 3 and a back surface 1b of the wafer 1T. In the second process, holes extending from the main surface 1a of the wafer 1T and reaching a wiring pattern of the wafer 3 are formed by a predetermined etching treatment. In the third process, the holes are filled with a conductive material to form through electrodes. The adhesive layer 4 has an etching rate of 1 to 2 μm/min in dry etching performed using an etching gas containing CF4, O2, and Ar at a volume ratio of 100:400:200 under predetermined conditions.

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