公开(公告)号：US07488630B2

公开(公告)日：2009-02-10

申请号：US11682638

申请日：2007-03-06

申请人： David J. Frank ,  Douglas C. La Tulipe, Jr. ,  Leathen Shi ,  Steven E. Steen ,  Anna W. Topol

发明人： David J. Frank ,  Douglas C. La Tulipe, Jr. ,  Leathen Shi ,  Steven E. Steen ,  Anna W. Topol

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L27/1203 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired.

摘要翻译： 提供了一种旨在通过在转移晶片上选择性修改FEOL膜堆来促进和/或简化制造层间通孔的方法的方法。 具体而言，本发明提供了一种方法，其中通过使用现有的层间接触掩模来限定在不期望的电介质层和金属层被选择性去除的区域，准备二维器件用于随后在正常FEOL工艺之间的过渡处的第三维中的集成 并重新填充中间线（MOL）兼容的电介质膜。 如所述的，本发明的方法与标准的FEOL / MOL集成方案兼容，并且其保证了在要形成层间接触的区域中特别是均匀的电介质膜堆叠，因此如果需要，可以选择直接的积分路径。

公开(公告)号：US07666723B2

公开(公告)日：2010-02-23

申请号：US11677598

申请日：2007-02-22

申请人： David J. Frank ,  Douglas C. La Tulipe, Jr. ,  Steven E. Steen ,  Anna W. Topol

发明人： David J. Frank ,  Douglas C. La Tulipe, Jr. ,  Steven E. Steen ,  Anna W. Topol

IPC分类号： H01L21/84

CPC分类号： H01L29/66477 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.

摘要翻译： 公开了向晶体管和相关晶体管布线的方法。 在一个实施例中，该方法包括一种向晶体管形成布线的方法，所述方法包括：使用作为预期布局的镜像的掩模在绝缘体上半导体（SOI）衬底上形成晶体管，所述形成包括形成 栅极和源极/漏极区域，所述SOI衬底包括绝缘体上半导体（SOI）层，掩埋绝缘体层和硅衬底; 在所述晶体管上形成介电层; 将介电层粘合到另一基底上; 将硅衬底从SOI衬底移除到掩埋绝缘体层; 从栅极的沟道侧形成与源极/漏极区域和栅极中的每一个的接触; 以及形成至少一条布线到栅极通道侧上的触点。

公开(公告)号：US07528056B2

公开(公告)日：2009-05-05

申请号：US11622543

申请日：2007-01-12

申请人： Meikei Ieong ,  Douglas C. La Tulipe, Jr. ,  Leathen Shi ,  Anna W. Topol ,  James Vichiconti ,  Albert M. Young

发明人： Meikei Ieong ,  Douglas C. La Tulipe, Jr. ,  Leathen Shi ,  Anna W. Topol ,  James Vichiconti ,  Albert M. Young

IPC分类号： H01L21/36 ,  H01L21/20

CPC分类号： H01L21/02658 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.

摘要翻译： 提供了一种制造应变绝缘体上半导体（SSOI）结构的成本有效和简单的方法，其避免了外延生长和随后的晶片接合处理步骤。 根据本发明，使用应变记忆技术在SOI衬底上产生应变半导体区域。 形成在应变半导体区域上的晶体管具有更高的载流子迁移率，因为Si区域已经变形。 本发明的方法包括（i）离子注入以产生薄的非晶化层，（ii）在非晶化层上沉积高应力膜，（iii）热退火以使非晶化层重结晶，和（iv）去除应力 电影。 由于在再结晶过程中SOI衬底处于应力状态，所以最终的半导体层也将受到应力。 应力的量和应力的极性（拉伸或压缩）可以通过应力膜的类型和厚度来控制。

公开(公告)号：US07875528B2

公开(公告)日：2011-01-25

申请号：US11672217

申请日：2007-02-07

申请人： Douglas C. La Tulipe, Jr. ,  Steven E. Steen ,  Anna W. Topol

发明人： Douglas C. La Tulipe, Jr. ,  Steven E. Steen ,  Anna W. Topol

IPC分类号： H01L21/30

CPC分类号： H01L23/544 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/67288 ,  H01L21/681 ,  H01L24/94 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01094 ,  H01L2924/14

摘要： A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying an alignment mark on each substrate; determining a location and a topography of each alignment mark using laser diffraction; creating an alignment model for each substrate based on the location and topography the alignment mark thereon; and bonding the first and second circuitry-including substrates together while aligning the first and second substrate based on the alignment model.

摘要翻译： 公开了一种用于键合包含两个电路的半导体衬底和相关阶段的方法，系统和程序产品。 在一个实施例中，一种键合包含两个电路的衬底的方法包括：提供用于保持包含第一电路的衬底的第一级和用于保持包括第二电路的衬底的第二级; 识别每个基板上的对准标记; 使用激光衍射确定每个对准标记的位置和形貌; 基于位置创建每个基板的对准模型，并在其上形成对准标记; 以及基于所述对准模型，将所述第一和第二基于电路的基板接合在一起，同时对准所述第一和第二基板。

公开(公告)号：US09318375B2

公开(公告)日：2016-04-19

申请号：US12540490

申请日：2009-08-13

申请人： Douglas C. La Tulipe, Jr. ,  Mark Todhunter Robson

发明人： Douglas C. La Tulipe, Jr. ,  Mark Todhunter Robson

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L27/06

CPC分类号： H01L21/76802 ,  H01L21/76804 ,  H01L27/0688 ,  H01L2224/80896 ,  H01L2224/9202

摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

摘要翻译： 通过多个电介质层开口形成高纵横比的方法，高纵横比导电通孔，形成三维集成电路的方法和三维集成电路。 所述方法包括形成至少四个电介质层的叠层，并且用对第二和第四电介质层选择性的工艺蚀刻第一和第三介电层，用对第一和第二电介质层选择的工艺蚀刻第二和第三介电层。 有利地，用于蚀刻第三介电层的工艺对第一介电层基本不具有选择性。

公开(公告)号：US07241696B2

公开(公告)日：2007-07-10

申请号：US10318606

申请日：2002-12-11

申请人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

发明人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

摘要翻译： 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体被覆盖层和电介质层覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体。 在溅射蚀刻的过程中，覆盖层被再沉积到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：US07001835B2

公开(公告)日：2006-02-21

申请号：US10707119

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

IPC分类号： H01L21/4763

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/76841 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.

摘要翻译： 集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和 通过硬掩模和ILD的中间层降低对准标记。 形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

公开(公告)号：US08940554B2

公开(公告)日：2015-01-27

申请号：US13359970

申请日：2012-01-27

申请人： Nathaniel C. Berliner ,  Kangguo Cheng ,  Toshiharu Furukawa ,  Douglas C. La Tulipe, Jr. ,  William R. Tonti

发明人： Nathaniel C. Berliner ,  Kangguo Cheng ,  Toshiharu Furukawa ,  Douglas C. La Tulipe, Jr. ,  William R. Tonti

IPC分类号： H01L21/306 ,  H01L21/66 ,  H01L21/302 ,  H01L21/762

CPC分类号： H01L22/20 ,  H01L21/302 ,  H01L21/30604 ,  H01L21/76254 ,  H01L22/12

摘要： A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.

摘要翻译： 一种制造具有均匀厚度的非常薄的绝缘上绝缘体（ETSOI）层的方法包括：测量多个位置上绝缘体上半导体（SOI）层的厚度; 确定所述多个位置中的每一个处的去除厚度; 以及在所述多个位置处注入离子。 基于多个位置中的每个位置处的去除厚度动态地进行植入。 该方法还包括氧化SOI层以形成氧化物层，并除去氧化物层。

公开(公告)号：US08765578B2

公开(公告)日：2014-07-01

申请号：US13489861

申请日：2012-06-06

申请人： Douglas C. La Tulipe, Jr. ,  Spyridon Skordas ,  Tuan A. Vo ,  Kevin R. Winstel

发明人： Douglas C. La Tulipe, Jr. ,  Spyridon Skordas ,  Tuan A. Vo ,  Kevin R. Winstel

IPC分类号： H01L21/30

CPC分类号： H01L25/50 ,  H01L23/562 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.

摘要翻译： 边缘保护键合半导体晶片的方法。 第二半导体晶片和第一半导体晶片通过接合层/界面附着，并且第二半导体晶片进行变薄处理。 作为稀化过程的一部分，第一保护层被施加到第二和第一半导体晶片的边缘。 第三半导体晶片通过接合层/界面附接到第二半导体晶片，并且第三半导体晶片经历变薄处理。 作为稀化过程的一部分，第二保护层被施加到第三半导体晶片的边缘并且在第一保护层上。 第一，第二和第三半导体晶片形成晶片叠层。 晶片堆叠被切成多个3D芯片，同时保持第一和第二保护层。

公开(公告)号：US08637953B2

公开(公告)日：2014-01-28

申请号：US12172452

申请日：2008-07-14

申请人： Douglas C. La Tulipe, Jr. ,  Sampath Purushothaman ,  James Vichiconti

发明人： Douglas C. La Tulipe, Jr. ,  Sampath Purushothaman ,  James Vichiconti

IPC分类号： H01L21/70

CPC分类号： H01L21/3065 ,  C23C16/402 ,  C23C16/513 ,  C23C16/56 ,  H01L21/02002 ,  H01L21/187 ,  H01L21/3221 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/77 ,  H01L24/94 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/06 ,  H01L2221/68377 ,  H01L2224/83121 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

摘要翻译： 描述了由其制造的三维集成器件和三维集成器件的制造。 施主晶片的器件侧涂覆有聚合物膜，并且将衬底侧暴露于氧化等离子体产生连续的SiO 2膜。 衬底侧的部分被选择性地涂覆聚合物膜，并且未涂覆区域的蚀刻除去至少大部分结晶衬底。 等离子体蚀刻工具将结晶衬底蚀刻到预定厚度内。 通过暴露于TMAH来蚀刻衬底侧的硅部分。 在蚀刻之后，施主半导体晶片由未被蚀刻的基板的部分支撑。 支撑结构允许施主半导体晶片在蚀刻区域内弯曲，以使得能够与受主晶片的器件表面保持一致并可靠地结合以形成三维集成器件。