公开(公告)号：US5352912A

公开(公告)日：1994-10-04

申请号：US792493

申请日：1991-11-13

申请人： Emmanuel F. Crabbe ,  David L. Harame ,  Bernard S. Meyerson ,  Gary Patton ,  Johannes M. C. Stork

发明人： Emmanuel F. Crabbe ,  David L. Harame ,  Bernard S. Meyerson ,  Gary Patton ,  Johannes M. C. Stork

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/737 ,  H01L29/161 ,  H01L29/72

CPC分类号： H01L29/7378 ,  H01L29/737 ,  Y10S438/936

摘要： A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region, a base region formed on the collector region, and a single-crystal emitter region grown on the base region by low temperature epitaxy. During the formation of the base region, a graded profile of 5-23% germanium is added to the base, as the distance to the collector region decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region, a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

摘要翻译： 本文描述了具有具有降低的电荷存储和可接受的电流增益的单晶发射极的异质结双极晶体管。 异质结晶体管包括集电极区域，形成在集电极区域上的基极区域和通过低温外延生长在基极区域上的单晶发射极区域。 在形成基极区域时，随着到集电极区域的距离减小，5-23％的锗的梯度分布被添加到基极中，从而随着接近集电极区域而减小基带隙。 此外，在形成发射极区域期间，随着与发射极 - 基极结的距离增加，0-20％锗的梯度轮廓被添加到发射极。 因此，发射极带隙随着与发射极 - 基极结更远地移动而减小。 上述分级曲线的结果是，在发射极接触处的发射极带隙比发射极 - 基极结处的基极带隙更窄。

公开(公告)号：US5119157A

公开(公告)日：1992-06-02

申请号：US664681

申请日：1991-03-05

申请人： David L. Harame ,  Bernard S. Meyerson ,  Johannes M. C. Stork

发明人： David L. Harame ,  Bernard S. Meyerson ,  Johannes M. C. Stork

IPC分类号： H01L21/20 ,  H01L21/74 ,  H01L21/8228 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/08

CPC分类号： H01L29/0821 ,  H01L21/743 ,  H01L21/82285 ,  H01L21/8238 ,  H01L27/0623

摘要： A P- semiconductor material substrate which has been ion-implanted with N-type dopants to form an N+ subcollector layer is annealed in Argon to further remove implant damage and drive the dopant ions deeper into the P substrate. Next a lightly doped N- epitaxial layer is grown on the N+ subcollector layer. This forms the blanket collector. A P- well region is formed by growing a pad oxide of 10 nm on the N-epi layer and a 200 nm layer of nitride is then deposited on top of the layer oxide. A photoresist etch mask is used to pattern the P- well region. A reactive ion etch is performed through the dielectric oxide and nitride layers, through the epitaxial layer and stopping in the subcollector layer. A layer of low temperature expitaxial material is grown over the structure using ultra-high vacuum/chemical vapor depositions such that the epitaxial layer extends above the surface of the epitaxial layer and includes a P+ heavily doped layer and a lightly P-doped surface layer. The heavily doped P+ layer provides the low resistance contact to the collector region and the lightly doped P-layer is the collector region and its thickness is determined by the diffusion of the heavily doped layer during the entire process.

摘要翻译： 已经用N型掺杂剂离子注入以形成N +子集电极层的P-半导体材料衬底在氩气中退火以进一步消除注入损伤并且将掺杂剂离子更深地驱动到P衬底中。 接下来，在N +子集电极层上生长轻掺杂的N外延层。 这形成了毯子收集器。 通过在N外延层上生长10nm的衬垫氧化物形成P-阱区，然后在层氧化物的顶部上沉积200nm的氮化物层。 使用光致抗蚀剂蚀刻掩模来图案化P-阱区域。 通过电介质氧化物层和氮化物层通过外延层进行反应离子蚀刻，并在子集电极层中停止。 使用超高真空/化学气相沉积在结构上生长一层低温外延材料，使得外延层在外延层的表面上延伸，并且包括P +重掺杂层和轻掺杂P掺杂表面层。 重掺杂的P +层向集电极区提供低电阻接触，轻掺杂的P层是集电极区，其厚度由整个工艺中重掺杂层的扩散决定。

公开(公告)号：US5101256A

公开(公告)日：1992-03-31

申请号：US658821

申请日：1991-02-22

申请人： David L. Harame ,  Johannes M. C. Stork

发明人： David L. Harame ,  Johannes M. C. Stork

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/732

CPC分类号： H01L29/66287 ,  H01L21/28525 ,  H01L29/66242 ,  H01L29/7322

摘要： A method of forming a bipolar transistor is provided, comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming a layer of insulative material over a surface of the first region; forming a layer of conductive material over the layer of insulative material; patterning the first and second layers to form a generally vertical sidewall bounding an exposed portion of the first region surface; and epitaxially depositing a base region of a second conductivity type over the exposed portion of the first region surface and the sidewall such that the base region is in electrical contact with the second region.

摘要翻译： 提供一种形成双极晶体管的方法，包括以下步骤：提供包括第一导电类型的第一区域的半导体衬底; 在所述第一区域的表面上形成绝缘材料层; 在绝缘材料层上形成导电材料层; 图案化第一和第二层以形成限定第一区域表面的暴露部分的大致垂直的侧壁; 以及在所述第一区域表面和所述侧壁的暴露部分上外延沉积第二导电类型的基极区域，使得所述基极区域与所述第二区域电接触。

公开(公告)号：US4951115A

公开(公告)日：1990-08-21

申请号：US319374

申请日：1989-03-06

申请人： David L. Harame ,  Gary L. Patton ,  Johannes M. C. Stork

发明人： David L. Harame ,  Gary L. Patton ,  Johannes M. C. Stork

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/732

CPC分类号： H01L21/82 ,  H01L27/0826

摘要： A complementary bipolar transistor structure having one symmetrical intrinsic region for both the NPN and PNP transistors and a method for fabricating the structure. The transistor structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. In the method, the sub-emitter and the sub-collector regions are formed by depositing a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, and forming the sub-collector by etching a shallow trench in the first layer and depositing semiconductor material of a second conductivity type by LTE and planarizing. The intrinsic regions for both of the transistors are formed by depositing a second layer of semiconductor material of the second conductivity type on the surface of the first layer and a third layer of semiconductor material of the first conductivity type on the surface of the second layer by either LTE or MBE. In one embodiment, the second and third layers are provided with a uniform vertical doping profile for one thickness of the layer and a graded doping profile for the remaining thickness in which the minimum doping level for both graded portions is at the junction between the second and third layers. The second layer forms the base and the third layer forms the collector for one transistor while at the same time the second layer forms a collector and the third layer forms the base for the other transistor. The performance of the intrinsic base and collector regions can be further improved by forming the second and third layers with a compound semiconductor material, such as, the compound of Si-Ge to create a heterojunction transistor. Device and intrinsic region isolation is effected by a combination of deep trench and shallow trench processes and reach-through regions for the sub-emitter and sub-collector are formed. A layer of polysilicon is deposited and selectively etched to form an extrinsic collector region for one transistor and extrinsic base regions for the other transistor. A further layer of single crystal silicon is deposited to form the extrinsic base region for one transistor and the emitter for the other transistor.

公开(公告)号：US5024957A

公开(公告)日：1991-06-18

申请号：US309510

申请日：1989-02-13

申请人： David L. Harame ,  Johannes M. C. Stork

发明人： David L. Harame ,  Johannes M. C. Stork

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/732

CPC分类号： H01L29/66287 ,  H01L29/66242 ,  H01L29/7322 ,  Y10S148/011 ,  Y10S148/154

摘要： A method of forming a bipolar transistor is provided, comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming a layer of insulative material over a surface of the first region; forming a layer of conductive material over the layer of insulative material; patterning the first and second layers to form a generally vertical sidewall bounding an exposed portion of the first region surface; and epitaxially depositing a base region of a second conductivity type over the exposed portion of the first region surface and the sidewall such that the base region is in electrical contact with the second region.

公开(公告)号：US09053939B2

公开(公告)日：2015-06-09

申请号：US13303248

申请日：2011-11-23

申请人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

发明人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

IPC分类号： H01L29/737 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/7371

摘要： A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.

摘要翻译： 异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。

公开(公告)号：US08921194B2

公开(公告)日：2014-12-30

申请号：US13294697

申请日：2011-11-11

申请人： David L. Harame ,  Qizhi Liu

发明人： David L. Harame ,  Qizhi Liu

IPC分类号： H01L21/331 ,  H01L21/8228 ,  H01L21/8224 ,  H01L29/66 ,  H01L27/082 ,  H01L29/737 ,  H01L29/10

CPC分类号： H01L29/735 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/16 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/7371

摘要： Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.

摘要翻译： 横向PNP双极结晶体管，用于制造横向PNP双极结型晶体管的方法，以及横向PNP双极结型晶体管的设计结构。 横向PNP双极结晶体管的发射极和集电极由通过选择性外延生长工艺形成的p型半导体材料组成。 源极和漏极各自直接接触用于形成发射极和集电极的器件区域的顶表面。 基部触点可以形成在顶表面上并且覆盖限定在器件区域内的n型基极。 发射极通过基座触点与收集器横向分开。 另一个基底接触可以形成在由基部与另一个基部接触分离的器件区域中。

公开(公告)号：US20140021587A1

公开(公告)日：2014-01-23

申请号：US13551971

申请日：2012-07-18

申请人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

发明人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/66 ,  H01L29/73

CPC分类号： H01L29/66234 ,  H01L29/0804 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/732

摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

摘要翻译： 本发明的方面提供了一种自对准发射极的双极晶体管。 在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间​​形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。

公开(公告)号：US08546240B2

公开(公告)日：2013-10-01

申请号：US13294610

申请日：2011-11-11

申请人： David L. Harame ,  Stephen E. Luce ,  Anthony K. Stamper

发明人： David L. Harame ,  Stephen E. Luce ,  Anthony K. Stamper

IPC分类号： H01L21/76 ,  H01L21/70

CPC分类号： H01L41/083 ,  G06F17/5068 ,  H01L21/84 ,  H01L27/1203 ,  H01L41/081 ,  H01L41/094 ,  H01L41/332 ,  H03H3/02 ,  H03H9/1007 ,  H03H9/173 ,  H03H2001/0064 ,  H03H2003/027 ,  H03H2009/155

摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes providing further sacrificial material in a trench of a lower wafer. The method further includes bonding the lower wafer to the insulator, under the single crystalline beam. The method further includes venting the sacrificial material and the further sacrificial material to form an upper cavity above the single crystalline beam and a lower cavity, below the single crystalline beam.

摘要翻译： 提供了与CMOS器件集成的体声波滤波器和/或体声波谐振器，制造方法和设计结构。 该方法包括从绝缘体上的硅层形成单晶束。 该方法包括在单晶束上提供绝缘体材料涂层。 该方法还包括通过绝缘体材料形成通孔。 该方法还包括在通孔和绝缘体材料上提供牺牲材料。 该方法还包括在牺牲材料上提供盖子。 该方法还包括在下晶片的沟槽中提供另外的牺牲材料。 该方法还包括在单晶束下将下晶片接合到绝缘体。 该方法还包括排出牺牲材料和另外的牺牲材料，以在单晶束之下形成单结晶束上方的上空腔和在单晶束下方的下腔。

公开(公告)号：US20110312147A1

公开(公告)日：2011-12-22

申请号：US12967268

申请日：2010-12-14

申请人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

发明人： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC分类号： H01L21/331

CPC分类号： H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

摘要： Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

摘要翻译： 公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。 晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定的导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是 随后形成。 可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。