公开(公告)号：US09166011B2

公开(公告)日：2015-10-20

申请号：US14328247

申请日：2014-07-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Seong Il Kim ,  Dong Min Kang ,  Sang Heung Lee ,  Ho Kyun Ahn ,  Hyung Sup Yoon ,  Byoung Gue Min ,  Jong Won Lim

IPC: H01L21/338 ,  H01L29/423 ,  H01L29/778 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L29/42312 ,  H01L21/28114 ,  H01L21/28587 ,  H01L21/28593 ,  H01L29/42316 ,  H01L29/66863 ,  H01L29/778 ,  H01L29/812

Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 μm or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.

Abstract translation: 公开了一种具有稳定的栅极结构的半导体器件及其制造方法，其中通过在栅极头的宽度方向上的栅极头附近还包括多个栅极脚来稳定栅极结构，以作为支撑体 在包括具有0.2μm或更小的长度的精细栅极脚的栅极结构中，并且栅极头具有预定尺寸。 因此，可以防止半导体器件的栅电极塌陷，并且在半导体器件的处理期间或之后提高半导体器件的可靠性。

公开(公告)号：US09899226B2

公开(公告)日：2018-02-20

申请号：US14658121

申请日：2015-03-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ho Kyun Ahn ,  Hae Cheon Kim ,  Jong Won Lim ,  Dong Min Kang ,  Yong Hwan Kwon ,  Seong Il Kim ,  Zin Sig Kim ,  Eun Soo Nam ,  Byoung Gue Min ,  Hyung Sup Yoon ,  Kyung Ho Lee ,  Jong Min Lee ,  Kyu Jun Cho

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/51 ,  H01L29/20 ,  H01L29/45

CPC classification number: H01L21/28264 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.

公开(公告)号：US09165896B2

公开(公告)日：2015-10-20

申请号：US14453969

申请日：2014-08-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hae Cheon Kim ,  Ho Kyun Ahn ,  Byoung Gue Min ,  Hyung Sup Yoon ,  Jong Won Lim

IPC: H01L33/00 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0225 ,  H01L2224/03466 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1423 ,  H01L2924/201 ,  H01L2924/37001 ,  H01L2224/45099

Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.

Abstract translation: 本发明涉及一种GaN晶体管及其制造方法，其中通过在源极，漏极和栅极的焊盘的边缘处形成欧姆金属层来改善焊盘的结构，因此 适于引线接合或背面通孔形成工艺。 因此，通过在制造GaN晶体管期间在焊盘的边缘处形成欧姆金属，可以增强焊盘的金属层与GaN基板之间的粘合力， 接合或背面通孔形成工艺，并提高器件的可靠性。