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    ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE
    1.
    发明申请
    ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE 失效
    芯片包装中的芯片载体的弹性模块映射

    公开(公告)号：US20140033148A1

    公开(公告)日：2014-01-30

    申请号：US13557386

    申请日：2012-07-25

    申请人： Erwin B. Cohen ,  Mark C.H. Lamorey ,  Marek A. Orlowski ,  Douglas O. Powell ,  David L. Questad ,  David B. Stone ,  Paul R. Walling

    发明人： Erwin B. Cohen ,  Mark C.H. Lamorey ,  Marek A. Orlowski ,  Douglas O. Powell ,  David L. Questad ,  David B. Stone ,  Paul R. Walling

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.

    摘要翻译： 计算机实现的方法提供了倒装芯片封装的芯片载体的弹性模量图。 将包括芯片载体的每个层的每个垂直对准子区域的电介质和导电设计元件的设计数据建模为弹簧以提供弹性模量图。 确定芯片载体的子区域的弹性模量在芯片接合期间识别可能的机械故障位置并冷却倒装芯片封装。 将焊料凸块修改为芯片载体可以减少施加到识别的可能的机械故障位置的应力。 修改芯片载体设计以减少与识别出的可能的机械故障位置相关联的子区域的刚度，还可减少芯片连接和冷却的应力。

    Elastic modulus mapping of a chip carrier in a flip chip package
    2.
    发明授权
    Elastic modulus mapping of a chip carrier in a flip chip package 失效
    芯片载体在倒装芯片封装中的弹性模量映射

    公开(公告)号：US08756546B2

    公开(公告)日：2014-06-17

    申请号：US13557386

    申请日：2012-07-25

    申请人： Erwin B. Cohen ,  Mark C. H. Lamorey ,  Marek A. Orlowski ,  Douglas O. Powell ,  David L. Questad ,  David B. Stone ,  Paul R. Walling

    发明人： Erwin B. Cohen ,  Mark C. H. Lamorey ,  Marek A. Orlowski ,  Douglas O. Powell ,  David L. Questad ,  David B. Stone ,  Paul R. Walling

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.

    摘要翻译： 计算机实现的方法提供了倒装芯片封装的芯片载体的弹性模量图。 将包括芯片载体的每个层的每个垂直对准子区域的电介质和导电设计元件的设计数据建模为弹簧以提供弹性模量图。 确定芯片载体的子区域的弹性模量在芯片接合期间识别可能的机械故障位置并冷却倒装芯片封装。 将焊料凸块修改为芯片载体可以减少施加到识别的可能的机械故障位置的应力。 修改芯片载体设计以减少与识别出的可能的机械故障位置相关联的子区域的刚度，还可减少芯片连接和冷却的应力。