公开(公告)号：US20060001170A1

公开(公告)日：2006-01-05

申请号：US10882855

申请日：2004-07-01

申请人： Fan Zhang ,  Tae Lee ,  Liang choo Hsia

发明人： Fan Zhang ,  Tae Lee ,  Liang choo Hsia

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L21/76882 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76886

摘要： An interconnect structure and method thereof comprising: a interconnect and a compound cap layer. The interconnect has a compound cap layer thereover. The interconnect is preferably comprised of copper. The compound cap layer is preferably comprised of a copper-metal (Cu-Me) compound or a metal; and is more preferably comprised of a Cu—Sn compound or Ni metal. A dielectric cap layer is formed over the compound cap layer. The compound cap layer can provide a barrier capping effect to the Cu to minimize the out-diffusion of Cu and therefore improve the electro-migration performance of Cu. The compound cap layer has excellent adhesion to dielectric cap layers, especially SiN and SiC dielectric cap layers.

摘要翻译： 一种互连结构及其方法，包括：互连和复合覆盖层。 互连在其上具有复合盖层。 互连优选地由铜组成。 化合物盖层优选由铜 - 金属（Cu-Me）化合物或金属组成; 更优选由Cu-Sn化合物或Ni金属构成。 在复合盖层之上形成电介质盖层。 复合盖层可以提供Cu的阻挡封盖作用以最小化Cu的扩散，从而提高Cu的电迁移性能。 复合覆盖层对电介质盖层，特别是SiN和SiC介电盖层具有优异的粘合性。

公开(公告)号：US07276440B2

公开(公告)日：2007-10-02

申请号：US10734423

申请日：2003-12-12

申请人： Fan Zhang ,  Bei Chao Zhang ,  Wuping Liu ,  Kho Liep Chok ,  Liang Choo Hsia ,  Tae Jong Lee ,  Juan Boon Tan ,  Xian Bin Wang

发明人： Fan Zhang ,  Bei Chao Zhang ,  Wuping Liu ,  Kho Liep Chok ,  Liang Choo Hsia ,  Tae Jong Lee ,  Juan Boon Tan ,  Xian Bin Wang

IPC分类号： H01L23/04

CPC分类号： H01L23/562 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.

摘要翻译： 根据本发明的目的，以“氧化物环”的形式提供了一种用于实施本发明的新设计和方法。 传统的模具设置有保护环或密封环，其围绕并隔离单个半导体管芯的有源表面积。 本发明的“氧化物环”围绕保护环或密封环，并以这种方式形成在管芯的锯切路径和单个化的半导体管芯的有源表面区域之间的机械应力释放缓冲器。

公开(公告)号：US07224060B2

公开(公告)日：2007-05-29

申请号：US10768796

申请日：2004-01-30

申请人： Fan Zhang ,  Kho Liep Chok ,  Tae Jong Lee ,  Xiaomei Bu ,  Meng Luo ,  Chian Yuh Sin ,  Yee Mei Foong ,  Luona Goh ,  Liang Choo Hsia ,  Huey Ming Chong

发明人： Fan Zhang ,  Kho Liep Chok ,  Tae Jong Lee ,  Xiaomei Bu ,  Meng Luo ,  Chian Yuh Sin ,  Yee Mei Foong ,  Luona Goh ,  Liang Choo Hsia ,  Huey Ming Chong

IPC分类号： H01L23/04

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

摘要： A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.

摘要翻译： 制造集成电路的方法提供了具有半导体器件的衬底，并且包括在衬底和半导体器件上形成金属间电介质层。 金属线形成在半导体器件的上方并与之接触，并且在金属间电介质层之上形成钝化层。 形成与金属线连接的接合焊盘。 通过钝化层和金属间电介质层形成具有侧壁钝化层的保护护套，并且位于金属线和集成电路的外边缘之间。

公开(公告)号：US08102054B2

公开(公告)日：2012-01-24

申请号：US12860946

申请日：2010-08-23

申请人： Bei Chao Zhang ,  Chim Seng Seet ,  Juan Boon Tan ,  Fan Zhang ,  Yong Chiang Ee ,  Bo Tao ,  Tong Qing Chen ,  Liang Choo Hsia

发明人： Bei Chao Zhang ,  Chim Seng Seet ,  Juan Boon Tan ,  Fan Zhang ,  Yong Chiang Ee ,  Bo Tao ,  Tong Qing Chen ,  Liang Choo Hsia

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L29/40

CPC分类号： H01L23/5329 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.

摘要翻译： 提出了一种形成半导体器件的方法。 该方法包括提供用其上形成的电介质层制备的衬底。 电介质层具有布置在电介质层上部的导线。 处理衬底以产生与导电线的顶表面不共面的电介质层的顶表面，以形成阶梯形状。

公开(公告)号：US20090315115A1

公开(公告)日：2009-12-24

申请号：US12214854

申请日：2008-06-23

申请人： Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

发明人： Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L29/7846

摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.

摘要翻译： 制造半导体器件的方法（和半导体器件）通过在STI区域中注入离子来提供浅沟槽隔离（STI）结构或区域。 在植入之后，区域（衬底材料和不同元素的离子）进行热退火，产生用于隔离两个相邻的场效应晶体管（FET）的电介质材料。 这消除了去除衬底材料以形成沟槽并用电介质材料重新填充沟槽的常规步骤。 将氮离子注入到邻近p型FET的STI区域中，对晶体管沟道区域施加压缩应力以增强晶体管性能。 将氧离子注入到与n型FET相邻的STI区域中，对晶体管沟道区域施加拉伸应力以增强晶体管性能。

公开(公告)号：US07524755B2

公开(公告)日：2009-04-28

申请号：US11358934

申请日：2006-02-22

申请人： Johnny Widodo ,  Bei Chao Zhang ,  Tong Qing Chen ,  Yong Kong Siew ,  Fan Zhang ,  San Leong Liew ,  John Sudijono ,  Liang Choo Hsia

发明人： Johnny Widodo ,  Bei Chao Zhang ,  Tong Qing Chen ,  Yong Kong Siew ,  Fan Zhang ,  San Leong Liew ,  John Sudijono ,  Liang Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05073 ,  H01L2224/05546 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/01039 ,  H01L2924/00

摘要： A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.

摘要翻译： 形成用于互连的CuSiN构成的阻挡层和盖的方法。 我们在半导体结构上的电介质层中提供互连开口。 通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。 然后，我们在填充互连开口的CuSiN层上形成互连。 我们可以在互连的顶部表面上形成CuSiN覆盖层。

公开(公告)号：US20070293039A1

公开(公告)日：2007-12-20

申请号：US11454397

申请日：2006-06-16

申请人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/288 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

摘要翻译： 公开了一种在电介质层中填充间隙的方法。 提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。 形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。 用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。 然后使用ECP来完成间隙的铜填充。 对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

公开(公告)号：US08598031B2

公开(公告)日：2013-12-03

申请号：US12568658

申请日：2009-09-28

申请人： Fan Zhang ,  Xiaomei Bu ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Fan Zhang ,  Xiaomei Bu ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76822 ,  H01L21/7684 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.

公开(公告)号：US07094669B2

公开(公告)日：2006-08-22

申请号：US10910499

申请日：2004-08-03

申请人： Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

发明人： Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

IPC分类号： H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

公开(公告)号：US07989338B2

公开(公告)日：2011-08-02

申请号：US11153747

申请日：2005-06-15

申请人： Fan Zhang ,  Kho Liep Chok ,  Alex See ,  Cheng-Cheh Tan ,  Xiaomei Bu ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Fan Zhang ,  Kho Liep Chok ,  Alex See ,  Cheng-Cheh Tan ,  Xiaomei Bu ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76859 ,  H01L21/76856 ,  H01L21/76864

摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.

摘要翻译： 用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。 掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。 在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。 稍后通过平坦化处理去除阻挡层。 在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。