公开(公告)号：US08691689B1

公开(公告)日：2014-04-08

申请号：US13689839

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Paul R. Besser ,  Sean X. Lin ,  Valli Arunachalam

IPC: H01L21/44

CPC classification number: H01L29/66575 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/665

Abstract: Methods for fabricating integrated circuits having low resistance device contacts are provided. One method includes depositing an ILD layer of insulating material overlying a device region that includes a metal silicide region. The ILD layer is etched to form a sidewall that defines a contact opening formed through the ILD layer exposing the metal silicide region. A liner is formed overlying the sidewall and the metal silicide region and defines an inner cavity in the contact opening. A copper layer is formed overlying the liner and at least partially filling the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract translation: 提供了制造具有低电阻器件触点的集成电路的方法。 一种方法包括沉积覆盖在包括金属硅化物区域的器件区域上的绝缘材料的ILD层。 蚀刻ILD层以形成侧壁，其限定通过暴露金属硅化物区域的ILD层形成的接触开口。 衬垫形成在侧壁和金属硅化物区域上方并且限定了接触开口中的内腔。 铜层形成在衬垫上方并且至少部分地填充内腔。 蚀刻铜层以露出衬套的上部，同时留下设置在内腔的底部中的铜部分。 铜无电沉积在铜部分上以填充内腔的剩余部分。

公开(公告)号：US20170125530A1

公开(公告)日：2017-05-04

申请号：US14927765

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Sean X. Lin

IPC: H01L29/417 ,  H01L21/288 ,  H01L29/45 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/288 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one etching process through the gate contact opening to remove a gate cap layer and to expose the gate structure, selectively growing a metal material that is conductively coupled to an upper surface of the gate structure such that the grown metal material contacts all of the sidewalls of the gate contact opening and an air space is formed between a bottom of the grown metal material and a conductive source/drain structure, and forming one or more conductive materials in the gate contact opening above the grown metal material.

公开(公告)号：US09087881B2

公开(公告)日：2015-07-21

申请号：US13785934

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean X. Lin ,  Xunyuan Zhang ,  Ming He ,  Larry Zhao ,  John Iacoponi ,  Kunaljeet Tanwar

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76847 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract translation: 在半导体衬底上形成的层间电介质中的沟槽由底部和侧壁限定。 铜屏障通过屏障上的铜生长促进衬里将沟槽排列。 沟槽有大量铜填充，并且在铜中包括空隙。 具有空隙的铜被除去，包括从侧壁，在底部留下无空隙的铜部分。 浸没在无电解铜浴中促进铜在无空隙铜部分顶部的向上生长，而不会向内侧壁铜生长，导致沟槽的无空隙铜填充。

公开(公告)号：US10109490B1

公开(公告)日：2018-10-23

申请号：US15627879

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean X. Lin ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  C23C16/06 ,  C22B23/00 ,  C01G51/00

Abstract: Methods for forming interconnects that include cobalt. An interconnect opening is formed in a dielectric layer that penetrates from a top surface of the dielectric layer into the dielectric layer. A first cobalt layer is formed at a bottom of the interconnect opening and partially fills the interconnect opening. A second cobalt layer is selectively deposited on the first cobalt layer and grows upwardly from the first cobalt layer at the bottom of the interconnect opening.

公开(公告)号：US09853110B2

公开(公告)日：2017-12-26

申请号：US14927765

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Sean X. Lin

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/288 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L21/288 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one etching process through the gate contact opening to remove a gate cap layer and to expose the gate structure, selectively growing a metal material that is conductively coupled to an upper surface of the gate structure such that the grown metal material contacts all of the sidewalls of the gate contact opening and an air space is formed between a bottom of the grown metal material and a conductive source/drain structure, and forming one or more conductive materials in the gate contact opening above the grown metal material.

公开(公告)号：US20140154877A1

公开(公告)日：2014-06-05

申请号：US13689844

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Paul R. Besser ,  Sean X. Lin ,  Valli Arunachalam

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

Abstract translation: 提供了具有低电阻金属栅极结构的集成电路制造方法。 一种方法包括在FET区域中形成的FET沟槽中形成金属栅叠层。 金属栅极堆叠被蚀刻以形成凹陷的金属栅极堆叠和凹陷。 凹槽由FET区域中的侧壁限定，并设置在凹陷金属栅极堆叠的上方。 衬套形成在侧壁和凹入的金属门叠层之上，并且在凹槽中限定内腔。 铜层形成在衬垫上方并且至少部分地填充内腔。 蚀刻铜层以露出衬套的上部，同时留下设置在内腔的底部中的铜部分。 铜无电沉积在铜部分上以填充内腔的剩余部分。

公开(公告)号：US09520321B2

公开(公告)日：2016-12-13

申请号：US14633914

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Sean X. Lin

IPC: H01L21/44 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76805 ,  H01L21/76829 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.

Abstract translation: 公开了用于制造具有自对准通孔的集成电路的集成电路和方法。 一种用于制造集成电路的方法包括形成覆盖半导体衬底的第一导电互连线。 该方法形成限定覆盖在第一导电互连线上的间隙的绝缘体帽。 在绝缘体盖上并在第一导电互连线上的间隙中沉积上层间绝缘材料。 将通孔蚀刻通过上层间介电材料并进入间隙以露出第一导电互连线。 该方法将导电材料沉积到通孔中以形成与第一导电互连线接触的导电通孔。

公开(公告)号：US20160254185A1

公开(公告)日：2016-09-01

申请号：US14633914

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Sean X. Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76805 ,  H01L21/76829 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.

Abstract translation: 公开了用于制造具有自对准通孔的集成电路的集成电路和方法。 一种用于制造集成电路的方法包括形成覆盖半导体衬底的第一导电互连线。 该方法形成限定覆盖在第一导电互连线上的间隙的绝缘体帽。 在绝缘体盖上并在第一导电互连线上的间隙中沉积上层间绝缘材料。 将通孔蚀刻通过上层间介电材料并进入间隙以露出第一导电互连线。 该方法将导电材料沉积到通孔中以形成与第一导电互连线接触的导电通孔。

公开(公告)号：US09263327B2

公开(公告)日：2016-02-16

申请号：US14310314

申请日：2014-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Sean X. Lin

IPC: H01L21/768 ,  H01L21/288

CPC classification number: H01L21/288 ,  C23C18/1834 ,  C23C18/40 ,  C23C18/405 ,  H01L21/76874 ,  H01L21/76877

Abstract: Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure.

Abstract translation: 提供了电路结构制造方法，其包括：图案化设置在衬底结构上的电介质层内的至少一个开口; 在介电层的至少一个开口内提供衬垫材料; 在衬垫材料的至少一部分上设置表面活性剂; 以及使用无电镀方法在所述衬里材料上沉积导电材料以形成导电结构，并且所述设置的表面活性剂抑制在所述导电结构内形成空隙。

公开(公告)号：US09054052B2

公开(公告)日：2015-06-09

申请号：US13903802

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent Licausi ,  Errol Todd Ryan ,  Ming He ,  Moosung M. Chae ,  Kunaljeet Tanwar ,  Larry Zhao ,  Christian Witt ,  Ailian Zhao ,  Sean X. Lin ,  Xunyuan Zhang

IPC: H01L21/314 ,  H01L21/308 ,  H01L21/32 ,  H01L29/06

CPC classification number: H01L21/314 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/06 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract translation: 提供了一种在制造期间减少对超低k层的损伤的方法的方法。 一方面，一种方法包括：提供含有填充有孔填充材料的孔的固化的超低k膜; 以及改变超低k膜的暴露表面以在超低k膜中提供改性层。 在另一方面，提供一种在超低k膜的表面上包含改性层的半导体器件。