公开(公告)号：US08951900B2

公开(公告)日：2015-02-10

申请号：US13870661

申请日：2013-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Axel Preusse ,  Norbert Schroeder ,  Uwe Stoeckgen

IPC: H01L21/20 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/7684 ,  H01L21/76819 ,  H01L21/76879

Abstract: The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material.

Abstract translation: 本公开尤其涉及一种说明性方法，其包括在半导体器件的接触电平的电介质材料中形成开口，并且在开口中选择性地沉积导电材料以在其中形成接触元件，所述触点 元件延伸到电路元件的接触区域，并且具有形成在开口外部和电介质材料之上的横向受限的多余部分。 所公开的方法还包括在电介质材料和接触元件之上形成牺牲材料层，牺牲材料层围绕横向限制的多余部分。 另外，该方法包括在存在牺牲材料的情况下对接触层的表面形貌进行平面化，从而从电介质材料上方去除侧向限制的多余部分。

公开(公告)号：US20140239503A1

公开(公告)日：2014-08-28

申请号：US13778558

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括形成电连接到器件的金属接触结构。 在金属接触结构上选择性地形成覆盖层，并且在覆盖层上沉积层间绝缘材料。 金属硬掩模被沉积并在层间电介质材料上图案化以限定层间电介质材料的暴露区域。 该方法蚀刻层间电介质材料的暴露区域以露出覆盖层的至少一部分。 该方法包括用蚀刻剂去除金属硬掩模，同时封盖层将金属接触结构与蚀刻剂物理分离。 沉积金属以形成通过封盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US20130237057A1

公开(公告)日：2013-09-12

申请号：US13870661

申请日：2013-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Axel Preusse ,  Norbert Schroeder ,  Uwe Stoeckgen

IPC: H01L21/768

CPC classification number: H01L21/7684 ,  H01L21/76819 ,  H01L21/76879

Abstract: The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material.

Abstract translation: 本公开尤其涉及一种说明性方法，其包括在半导体器件的接触电平的电介质材料中形成开口，并且在开口中选择性地沉积导电材料以在其中形成接触元件，所述触点 元件延伸到电路元件的接触区域，并且具有形成在开口外部和电介质材料之上的横向受限的多余部分。 所公开的方法还包括在电介质材料和接触元件之上形成牺牲材料层，牺牲材料层围绕横向限制的多余部分。 另外，该方法包括在存在牺牲材料的情况下对接触层的表面形貌进行平面化，从而从电介质材料上方去除侧向限制的多余部分。

公开(公告)号：US20150097291A1

公开(公告)日：2015-04-09

申请号：US14570617

申请日：2014-12-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括金属接触结构，形成在金属接触结构上的导电覆盖层，以及通过导电覆盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US08932911B2

公开(公告)日：2015-01-13

申请号：US13778558

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L21/4763 ,  H01L21/82 ,  H01L21/311 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括形成电连接到器件的金属接触结构。 在金属接触结构上选择性地形成覆盖层，并且在覆盖层上沉积层间绝缘材料。 金属硬掩模被沉积并在层间电介质材料上图案化以限定层间电介质材料的暴露区域。 该方法蚀刻层间电介质材料的暴露区域以露出覆盖层的至少一部分。 该方法包括用蚀刻剂去除金属硬掩模，同时封盖层将金属接触结构与蚀刻剂物理分离。 沉积金属以形成通过封盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US09620453B2

公开(公告)日：2017-04-11

申请号：US14512850

申请日：2014-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Axel Preusse ,  Romy Liske ,  Marcus Wislicenus ,  Robert Krause ,  Lukas Gerlich ,  Benjamin Uhlig ,  Sascha Bott

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/285 ,  H01L21/288 ,  C25D7/12 ,  C23C18/16 ,  C23C18/54 ,  C25D3/38

CPC classification number: H01L23/53252 ,  C23C18/1653 ,  C23C18/54 ,  C25D3/38 ,  C25D7/123 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes providing a semiconductor structure including a recess. The recess includes at least one of a contact via and a trench. A layer of a first metal is deposited over the semiconductor structure. An electroless deposition process is performed. The electroless deposition process removes a first portion of the layer of first metal from the semiconductor structure and deposits a first layer of a second metal over the semiconductor structure. An electroplating process is performed. The electroplating process deposits a second layer of the second metal over the first layer of second metal. A second portion of the layer of first metal remains in the semiconductor structure.

公开(公告)号：US20160104638A1

公开(公告)日：2016-04-14

申请号：US14512850

申请日：2014-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Axel Preusse ,  Romy Liske ,  Marcus Wislicenus ,  Robert Krause ,  Lukas Gerlich ,  Benjamin Uhlig ,  Sascha Bott

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53252 ,  C23C18/1653 ,  C23C18/54 ,  C25D3/38 ,  C25D7/123 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes providing a semiconductor structure including a recess. The recess includes at least one of a contact via and a trench. A layer of a first metal is deposited over the semiconductor structure. An electroless deposition process is performed. The electroless deposition process removes a first portion of the layer of first metal from the semiconductor structure and deposits a first layer of a second metal over the semiconductor structure. An electroplating process is performed. The electroplating process deposits a second layer of the second metal over the first layer of second metal. A second portion of the layer of first metal remains in the semiconductor structure.

Abstract translation: 一种方法包括提供包括凹部的半导体结构。 凹部包括接触通孔和沟槽中的至少一个。 在半导体结构上沉积第一金属层。 执行无电沉积工艺。 无电沉积工艺从半导体结构去除第一金属层的第一部分并且在半导体结构上沉积第二金属的第一层。 进行电镀工艺。 电镀工艺将第二金属的第二层沉积在第二金属的第一层上。 第一金属层的第二部分保留在半导体结构中。

公开(公告)号：US09305878B2

公开(公告)日：2016-04-05

申请号：US14570617

申请日：2014-12-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L23/522 ,  H01L23/485 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括金属接触结构，形成在金属接触结构上的导电覆盖层，以及通过导电覆盖层电连接到金属接触结构的导电通孔。