利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

17 条记录 (耗时 0.027 秒)

    METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A PHOTODETECTOR
    5.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A PHOTODETECTOR 审中-公开
    用于形成具有光电转换器的半导体器件的方法

    公开(公告)号：US20110027950A1

    公开(公告)日：2011-02-03

    申请号：US12510358

    申请日：2009-07-28

    申请人： Robert E. Jones ,  Dean J. Denning ,  Gregory S. Spencer

    发明人： Robert E. Jones ,  Dean J. Denning ,  Gregory S. Spencer

    IPC分类号： H01L27/12

    CPC分类号： H01L27/14689 ,  H01L27/0617 ,  H01L27/14643

    摘要： A method is provided for integrating a germanium photodetector with a CMOS circuit. The method comprises: forming first and second isolation regions in a silicon substrate; forming a gate electrode in the first isolation region; implanting source/drain extensions in the silicon substrate adjacent to the gate electrode; forming a first sidewall spacer on the gate electrode; implanting source/drain regions in the silicon substrate; removing the first sidewall spacer from the gate electrode; forming a first protective layer over the first and second isolation regions; removing a portion of the first protective layer to form an opening over the second isolation region; forming a semiconductor material comprising germanium in the opening; forming a second protective layer over the first and second isolation regions; selectively removing the first and second protective layers from the first isolation region; and forming contacts to the transistor and to the semiconductor material.

    摘要翻译： 提供了一种用于将锗光电检测器与CMOS电路集成的方法。 该方法包括：在硅衬底中形成第一和第二隔离区; 在所述第一隔离区域中形成栅电极; 在邻近栅电极的硅衬底中注入源极/漏极延伸部分; 在所述栅电极上形成第一侧壁间隔物; 在硅衬底中注入源/漏区; 从所述栅极电极去除所述第一侧壁间隔物; 在所述第一和第二隔离区域上形成第一保护层; 去除所述第一保护层的一部分以在所述第二隔离区域上形成开口; 在开口中形成包含锗的半导体材料; 在所述第一和第二隔离区域上形成第二保护层; 从第一隔离区选择性地去除第一和第二保护层; 以及形成与晶体管和半导体材料的接触。

    Temperature controlled process for the epitaxial growth of a film of material
    7.
    发明授权
    Temperature controlled process for the epitaxial growth of a film of material 失效
    用于材料膜外延生长的温度控制过程

    公开(公告)号：US5308788A

    公开(公告)日：1994-05-03

    申请号：US49645

    申请日：1993-04-19

    申请人： Jon T. Fitch ,  Dean J. Denning ,  Carlos A. Mazure

    发明人： Jon T. Fitch ,  Dean J. Denning ,  Carlos A. Mazure

    IPC分类号： C30B25/10 ,  C30B25/14 ,  H01L21/205 ,  H01L21/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262

    摘要： A ramp activated low temperature quality epitaxial growth process. A substrate is pre-conditioned and a passivation layer overlying the substrate surface is formed. The substrate is introduced into a process chamber having a controlled temperature. A process chamber purge technique is used to remove oxygen and contaminants from the process chamber before epitaxial growth begins. A process gas, which has an epitaxial growth species, a process chamber purging species and other possible species, is introduced into the process chamber at a low temperature. The process gas and the passivation layer keep the process chamber environment and the substrate surface free from contamination and free from native oxide growth before and, in some cases, during epitaxial growth. The process chamber temperature is gradually elevated to initiate a quality epitaxial growth by starting growth relative to decomposition of the passivation layer.

    摘要翻译： 斜坡激活了低温质量外延生长过程。 预处理衬底并形成覆盖衬底表面的钝化层。 将衬底引入具有受控温度的处理室中。 在外延生长开始之前，使用处理室吹扫技术从处理室中除去氧气和污染物。 具有外延生长物质的处理气体，处理室清洗物质和其它可能的物质在低温下被引入处理室。 工艺气体和钝化层保持处理室环境和衬底表面在外延生长之前和/或在某些情况下在外延生长期间没有污染并且没有自然氧化物生长。 通过相对于钝化层的分解开始生长，处理室温度逐渐升高以引发质量外延生长。

    Method of forming a semiconductor device barrier layer
    8.
    发明授权
    Method of forming a semiconductor device barrier layer 有权
    形成半导体器件阻挡层的方法

    公开(公告)号：US06451181B1

    公开(公告)日：2002-09-17

    申请号：US09261879

    申请日：1999-03-02

    申请人： Dean J. Denning ,  Sam S. Garcia ,  Bradley P. Smith ,  Daniel J. Loop ,  Gregory Norman Hamilton ,  Md. Rabiul Islam ,  Brian G. Anthony

    发明人： Dean J. Denning ,  Sam S. Garcia ,  Bradley P. Smith ,  Daniel J. Loop ,  Gregory Norman Hamilton ,  Md. Rabiul Islam ,  Brian G. Anthony

    IPC分类号： C23C1434

    CPC分类号： H01L21/76846 ,  C23C14/50 ,  C23C14/564 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76865 ,  H01L21/76871

    摘要： A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

    摘要翻译： 用于形成改进的铜镶嵌互连（图11）的方法开始于在腔室（10）中的镶嵌结构上执行RF预清洗操作（408）。 RF预清洁器围绕结构的角部（210a和206a），以减少空隙并改善步骤覆盖，同时不显着地从下面暴露的铜互连表面（202a）去除铜原子。 然后沉积钽屏障（220），其中一部分钽屏障比钽屏障的另一部分更具拉伸力。 在形成阻挡层（220）之后，在阻挡层的顶部上形成铜籽晶层（222）。 在使用改进的夹具（85）夹紧晶片的同时形成铜层，其减少了在晶片边缘处的铜剥离和污染。 然后使用铜电镀和化学机械抛光（CMP）工艺来完成铜互连结构。

    Method for forming a conductive structure having a composite or amorphous barrier layer
    9.
    发明授权
    Method for forming a conductive structure having a composite or amorphous barrier layer 失效
    用于形成具有复合或无定形阻挡层的导电结构的方法

    公开(公告)号：US06136682A

    公开(公告)日：2000-10-24

    申请号：US954149

    申请日：1997-10-20

    申请人： Rama I. Hegde ,  Dean J. Denning ,  Jeffrey L. Klein ,  Philip J. Tobin

    发明人： Rama I. Hegde ,  Dean J. Denning ,  Jeffrey L. Klein ,  Philip J. Tobin

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/4763

    CPC分类号： H01L21/76876 ,  H01L21/76807 ,  H01L21/76843 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002

    摘要： A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorphous tantalum nitride layer. A collective thickness of the tantalum nitride and titanium nitride layers 12 and 14 is roughly 400 angstroms or less. A copper material 16 is then deposited on top of the amorphous titanium nitride wherein the composite tantalum nitride layer 12 and titanium nitride layer 14 effectively prevents copper from diffusion from the layer 16 to the layer 10.

    摘要翻译： A形成改进的铜阻挡层的方法是通过提供含硅层（10）开始的。 然后使用物理气相沉积工艺来形成薄的氮化钽非晶层（12）。 然后在非晶氮化钽层上沉积薄的无定形氮化钛层（14）。 氮化钽和氮化钛层12和14的总体厚度大致为400埃或更小。 然后将铜材料16沉积在非晶氮化钛的顶部上，其中复合氮化钽层12和氮化钛层14有效地防止铜从层16扩散到层10。

    Method and apparatus for forming a layer on a substrate
    10.
    发明授权
    Method and apparatus for forming a layer on a substrate 失效
    在基板上形成层的方法和装置

    公开(公告)号：US06500315B1

    公开(公告)日：2002-12-31

    申请号：US09631400

    申请日：2000-08-03

    申请人： Valli Arunachalam ,  Peter L. G. Ventzek ,  Dean J. Denning ,  John C. Arnold

    发明人： Valli Arunachalam ,  Peter L. G. Ventzek ,  Dean J. Denning ,  John C. Arnold

    IPC分类号： C23C1600

    CPC分类号： H01J37/321 ,  C23C14/352 ,  C23C14/358 ,  H01L21/02112 ,  H01L21/02266 ,  H01L21/31629

    摘要： A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).

    摘要翻译： 公开了一种在衬底上形成层的方法和装置。 根据一个实施例，将衬底（901）放置在包括线圈（16）和屏蔽（14）的腔室（30）中，其中线圈和屏蔽件通过隔离/支撑构件（32）电隔离， 具有与所述线圈的表面基本相邻的第一表面（321），并具有与所述屏蔽件的表面基本相邻的第二表面（322）。 然后在衬底（901）上沉积一层（1002,1102）。