公开(公告)号：US10243047B2

公开(公告)日：2019-03-26

申请号：US15372929

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L29/06 ,  H01L23/66 ,  H01L21/762 ,  H01L29/78 ,  H01L25/18 ,  H01L21/764 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to active and passive radio frequency (RF) components with deep trench isolation structures and methods of manufacture. The structure includes a bulk high resistivity wafer with a deep trench isolation structure having a depth deeper than a maximum depletion depth at worst case voltage bias difference between devices which are formed on the bulk high resistivity wafer.

公开(公告)号：US09953831B1

公开(公告)日：2018-04-24

申请号：US15385949

申请日：2016-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Shank ,  Randall Brault ,  Jay Burnham ,  John J. Ellis-Monaghan

IPC: H01L27/01 ,  H01L21/02 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/02332 ,  H01L21/02362 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/513 ,  H01L29/66628

Abstract: Device structures for field-effect transistors and methods of forming device structures for a field-effect transistor. A first dielectric layer is formed on a semiconductor layer and nitrided. A nitrogen-enriched layer is formed at a first interface between the first dielectric layer and the semiconductor layer. Another nitrogen-enriched layer is formed at a second interface between the semiconductor layer and a second dielectric layer. Device structures may include field-effect transistors that include one, both, and/or neither of the nitrogen-enriched layers.

公开(公告)号：US09806221B2

公开(公告)日：2017-10-31

申请号：US15441345

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/105 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/0392 ,  H01L31/0312 ,  H01L31/0352 ,  H01L31/103

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

公开(公告)号：US09799693B2

公开(公告)日：2017-10-24

申请号：US15215674

申请日：2016-07-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146 ,  H01L21/762 ,  H01L31/0232

CPC classification number: H01L27/14632 ,  G02B6/4202 ,  H01L21/76224 ,  H01L21/76283 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/101

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

公开(公告)号：US20170062647A1

公开(公告)日：2017-03-02

申请号：US15227081

申请日：2016-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L31/18 ,  H01L31/0203 ,  H01L31/028 ,  H01L31/0216 ,  H01L27/144 ,  H01L31/105

CPC classification number: H01L31/1808 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14629 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1872

Abstract: Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed on a dielectric layer such that it is in contact with a monocrystalline semiconductor core of an optical waveguide. The light-absorbing layer is then encapsulated in one or more strain-relief layers and a rapid melting growth (RMG) process is performed to crystallize the light-absorbing layer. The strain-relief layer(s) are tuned for controlled strain relief so that, during the RMG process, the light-absorbing layer remains crack-free. The strain-relief layer(s) are then removed and an encapsulation layer is formed over the light-absorbing layer (e.g., filling in surface pits that developed during the RMG process). Subsequently, dopants are implanted through the encapsulation layer to form diffusion regions for PIN diode(s). Since the encapsulation layer is relatively thin, desired dopant profiles can be achieved within the diffusion regions.

Abstract translation: 公开了一种形成光电检测器和光电检测器结构的方法。 在该方法中，在电介质层上形成多晶或非晶光吸收层，使其与光波导的单晶半导体芯接触。 然后将光吸收层封装在一个或多个应变消除层中，并进行快速熔融生长（RMG）工艺以使光吸收层结晶。 调节应变消除层以控制应变消除，使得在RMG过程期间，光吸收层保持无裂纹。 然后去除应变消除层，并且在光吸收层上形成封装层（例如，填充在RMG工艺期间产生的表面凹坑中）。 随后，通过封装层注入掺杂剂以形成用于PIN二极管的扩散区域。 由于封装层相对较薄，所以可以在扩散区域内实现所需的掺杂分布。

公开(公告)号：US20170054049A1

公开(公告)日：2017-02-23

申请号：US14830870

申请日：2015-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/109 ,  H01L31/0352 ,  H01L31/18 ,  H01L31/028

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

Abstract translation: 各种具体实施方案包括形成光电检测器的方法，包括：形成包括设置在掺杂硅（Si）层和锗层（Ge）之间的阻挡层的结构，所述阻挡层包括结晶窗口; 并且退火该结构以通过晶化窗口将Ge转化为硅锗（SiGe）的第一组成和掺杂Si至SiGe的第二组成。

公开(公告)号：US20160343759A1

公开(公告)日：2016-11-24

申请号：US15215674

申请日：2016-07-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146

CPC classification number: H01L27/14632 ,  G02B6/4202 ,  H01L21/76224 ,  H01L21/76283 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/101

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

公开(公告)号：US10903316B2

公开(公告)日：2021-01-26

申请号：US16575675

申请日：2019-09-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli

IPC: H01L21/764 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US10424664B2

公开(公告)日：2019-09-24

申请号：US15378990

申请日：2016-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.

公开(公告)号：US10340352B2

公开(公告)日：2019-07-02

申请号：US15458482

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Alvin J. Joseph ,  John J. Ellis-Monaghan

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L21/28 ,  H01L21/265 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.