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1.发明授权Methods of forming strained-semiconductor-on-insulator finFET device structures 有权形成应变半导体绝缘体finFET器件结构的方法公开(公告)号：US07074623B2
公开(公告)日：2006-07-11
申请号：US10456708
申请日：2003-06-06
申请人： Anthony J. Lochtefeld , Thomas A. Langdo , Richard Hammond , Matthew T. Currie , Glyn Braithwaite , Eugene A. Fitzgerald
发明人： Anthony J. Lochtefeld , Thomas A. Langdo , Richard Hammond , Matthew T. Currie , Glyn Braithwaite , Eugene A. Fitzgerald
IPC分类号： H01L21/335 , H01L21/00 , H01L21/84 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/785 , H01L21/76254 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/66795 , H01L29/66916 , H01L29/7842 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。
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公开(公告)号：US08809835B2
公开(公告)日：2014-08-19
申请号：US13568944
申请日：2012-08-07
IPC分类号： H01L29/737 , H01L29/10
CPC分类号： H01L29/7378 , H01L27/0617 , H01L27/092 , H01L29/1054 , H01L29/517 , H01L29/518 , H01L29/78654 , H03B5/1203 , H03B5/1209 , H03B5/1212 , H03B5/1215 , H03B5/1221 , H03B5/1228 , H03B5/1243 , H03K3/354 , H03L7/093 , H03L7/099
摘要： Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.
摘要翻译： 用于处理射频（“RF”）和微波信号的电路使用具有设置在一个或多个平坦化衬底层上的一个或多个应变沟道层的场效应晶体管（“FET”）来制造。 具有这种结构的FET对于例如跨导和噪声系数显示出改善的值。 诸如例如压控振荡器（“VCO”），使用这些FET构建的低噪声放大器（“LNA”）和锁相环（“PLL”）的RF电路也表现出增强的性能。
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公开(公告)号：US08247798B2
公开(公告)日：2012-08-21
申请号：US13017694
申请日：2011-01-31
IPC分类号： H01L31/00
CPC分类号： H01L29/7378 , H01L27/0617 , H01L27/092 , H01L29/1054 , H01L29/517 , H01L29/518 , H01L29/78654 , H03B5/1203 , H03B5/1209 , H03B5/1212 , H03B5/1215 , H03B5/1221 , H03B5/1228 , H03B5/1243 , H03K3/354 , H03L7/093 , H03L7/099
摘要： Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.
摘要翻译： 用于处理射频（“RF”）和微波信号的电路使用具有设置在一个或多个平坦化衬底层上的一个或多个应变沟道层的场效应晶体管（“FET”）来制造。 具有这种结构的FET对于例如跨导和噪声系数显示出改善的值。 诸如例如压控振荡器（“VCO”），使用这些FET构建的低噪声放大器（“LNA”）和锁相环（“PLL”）的RF电路也表现出增强的性能。
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公开(公告)号：US07109516B2
公开(公告)日：2006-09-19
申请号：US11211933
申请日：2005-08-25
申请人： Thomas A. Langdo , Matthew T. Currie , Glyn Braithwaite , Richard Hammond , Anthony J. Lochtefeld , Eugene A. Fitzgerald
发明人： Thomas A. Langdo , Matthew T. Currie , Glyn Braithwaite , Richard Hammond , Anthony J. Lochtefeld , Eugene A. Fitzgerald
IPC分类号： H01L31/0328 , H01L29/745 , H01L27/148 , H01L29/80 , H01L21/332 , H01L21/00
CPC分类号： H01L29/785 , H01L21/76254 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/66795 , H01L29/66916 , H01L29/7842 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。
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5.发明授权Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication 有权具有减少的位错缺陷密度的晶格不匹配的半导体结构和用于器件制造的相关方法公开(公告)号：US08324660B2
公开(公告)日：2012-12-04
申请号：US12845593
申请日：2010-07-28
申请人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
发明人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
IPC分类号： H01L21/02
CPC分类号： H01L21/02609 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02538 , H01L21/02612 , H01L21/02639 , H01L21/02647 , H01L21/28255 , H01L21/28264 , H01L21/8258 , H01L27/0605 , H01L27/092 , H01L29/04 , H01L29/1054 , H01L29/16 , H01L29/20 , H01L29/66666 , H01L29/66795 , H01L29/778 , H01L29/78 , H01L29/7827 , H01L29/7835 , H01L29/7848 , H01L29/785 , H01L29/78687 , H01L31/028 , H01L31/0304 , H01L31/036 , H01L31/1808 , H01L33/20 , H01L33/30 , H01L33/34 , Y02E10/50
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。
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6.发明申请Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication 有权晶格不匹配的半导体结构具有减少的位错缺陷密度和相关的器件制造方法公开(公告)号：US20110049568A1
公开(公告)日：2011-03-03
申请号：US12845593
申请日：2010-07-28
申请人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
发明人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
IPC分类号： H01L29/06
CPC分类号： H01L21/02609 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02538 , H01L21/02612 , H01L21/02639 , H01L21/02647 , H01L21/28255 , H01L21/28264 , H01L21/8258 , H01L27/0605 , H01L27/092 , H01L29/04 , H01L29/1054 , H01L29/16 , H01L29/20 , H01L29/66666 , H01L29/66795 , H01L29/778 , H01L29/78 , H01L29/7827 , H01L29/7835 , H01L29/7848 , H01L29/785 , H01L29/78687 , H01L31/028 , H01L31/0304 , H01L31/036 , H01L31/1808 , H01L33/20 , H01L33/30 , H01L33/34 , Y02E10/50
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。
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7.发明申请Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication 审中-公开具有减少的位错缺陷密度的晶格不匹配的半导体结构和用于器件制造的相关方法公开(公告)号：US20070267722A1
公开(公告)日：2007-11-22
申请号：US11436062
申请日：2006-05-17
申请人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
发明人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
IPC分类号： H01L29/06
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/66666 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/785 , H01L29/78687 , H01L31/1808 , Y02E10/50
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。
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8.发明申请Methods for forming structures including strained-semiconductor-on-insulator devices 审中-公开用于形成包括应变绝缘体上半导体器件的结构的方法公开(公告)号：US20060197126A1
公开(公告)日：2006-09-07
申请号：US11416423
申请日：2006-05-02
申请人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Glyn Braithwaite , Eugene Fitzgerald
发明人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Glyn Braithwaite , Eugene Fitzgerald
IPC分类号： H01L21/8234 , H01L29/76 , H01L31/00
CPC分类号： H01L29/785 , H01L21/76254 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/66795 , H01L29/66916 , H01L29/7842 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。
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9.发明申请Methods for forming double gate strained-semiconductor-on-insulator device structures 审中-公开用于形成双栅应变半导体绝缘体上器件结构的方法公开(公告)号：US20060197125A1
公开(公告)日：2006-09-07
申请号：US11415784
申请日：2006-05-02
申请人： Thomas Langdo , Matthew Currie , Glyn Braithwaite , Richard Hammond , Anthony Lochtefeld , Eugene Fitzgerald
发明人： Thomas Langdo , Matthew Currie , Glyn Braithwaite , Richard Hammond , Anthony Lochtefeld , Eugene Fitzgerald
IPC分类号： H01L21/8234 , H01L29/76 , H01L31/00
CPC分类号： H01L29/785 , H01L21/76254 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/66795 , H01L29/66916 , H01L29/7842 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。
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公开(公告)号：US06680496B1
公开(公告)日：2004-01-20
申请号：US10191006
申请日：2002-07-08
申请人： Richard Hammond , Glyn Braithwaite
发明人： Richard Hammond , Glyn Braithwaite
IPC分类号： H01L2978
CPC分类号： H01L29/802
摘要： Transistors including a buried channel layer intermediate to a source and a drain and a surface layer intermediate to the buried layer and a gate are operated so as to cause current between the source and the drain to flow predominately through the buried channel layer by applying a back-bias voltage to the transistor. The back-bias voltage modulates a free charge carrier density distribution in the buried layer and in the surface layer.
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