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    Semiconductor structures, DRAM cells and electronic systems
    1.
    发明申请
    Semiconductor structures, DRAM cells and electronic systems 失效
    半导体结构，DRAM单元和电子系统

    公开(公告)号：US20050042824A1

    公开(公告)日：2005-02-24

    申请号：US10945774

    申请日：2004-09-20

    申请人： Shenlin Chen ,  Trung Doan ,  Guy Blalock ,  Lyle Breiner ,  Er-Xuan Ping

    发明人： Shenlin Chen ,  Trung Doan ,  Guy Blalock ,  Lyle Breiner ,  Er-Xuan Ping

    IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L23/58

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/84 ,  Y10S438/964

    摘要： The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

    摘要翻译： 本发明包括形成坚固的含半导体的表面的方法。 在衬底上形成第一半导体层，并且在第一半导体层上形成第二半导体层。 随后，在第二半导体层上形成第三半导体层，并且在第三半导体层上形成含半导体的种子。 将种子退火以形成坚固的含半导体的表面。 第一，第二和第三半导体层是公共堆叠的一部分，并且可以在电容器结构的存储节点内一起使用。 本发明还包括包括粗糙表面的半导体结构。 坚固的表面可以是例如坚固的硅。

    DRAM cells
    2.
    发明申请
    DRAM cells 失效
    DRAM单元

    公开(公告)号：US20060228857A1

    公开(公告)日：2006-10-12

    申请号：US11449433

    申请日：2006-06-07

    申请人： Shenlin Chen ,  Trung Doan ,  Guy Blalock ,  Lyle Breiner ,  Er-Xuan Ping

    发明人： Shenlin Chen ,  Trung Doan ,  Guy Blalock ,  Lyle Breiner ,  Er-Xuan Ping

    IPC分类号： H01L21/8242 ,  H01L21/20

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/84 ,  Y10S438/964

    摘要： The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

    摘要翻译： 本发明包括形成坚固的含半导体的表面的方法。 在衬底上形成第一半导体层，并且在第一半导体层上形成第二半导体层。 随后，在第二半导体层上形成第三半导体层，并且在第三半导体层上形成含半导体的种子。 将种子退火以形成坚固的含半导体的表面。 第一，第二和第三半导体层是公共堆叠的一部分，并且可以在电容器结构的存储节点内一起使用。 本发明还包括包括粗糙表面的半导体结构。 坚固的表面可以是例如坚固的硅。

    Planarization process for semiconductor substrates
    4.
    发明申请
    Planarization process for semiconductor substrates 审中-公开
    半导体衬底的平面化工艺

    公开(公告)号：US20060249723A1

    公开(公告)日：2006-11-09

    申请号：US11484809

    申请日：2006-07-11

    申请人： Trung Doan ,  Guy Blalock ,  Mark Durcan ,  Scott Meikle

    发明人： Trung Doan ,  Guy Blalock ,  Mark Durcan ,  Scott Meikle

    IPC分类号： H01L47/00 ,  C03C15/00

    CPC分类号： H01L21/31053

    摘要： A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.

    摘要翻译： 使用改进的化学机械平面化工艺制造半导体器件的方法，用于对其上形成半导体器件的晶片的表面进行平坦化。 改进的化学机械平面化处理包括从晶片表面上的可变形涂层形成平坦的平坦表面，其填充在通过化学机械平面化工艺在表面平坦化之前的表面凹凸之间。

    Electronic systems
    5.
    发明申请
    Electronic systems 失效

    公开(公告)号：US20060237763A1

    公开(公告)日：2006-10-26

    申请号：US11449431

    申请日：2006-06-07

    申请人： Shenlin Chen ,  Trung Doan ,  Guy Blalock ,  Lyle Breiner ,  Er-Xuan Ping

    发明人： Shenlin Chen ,  Trung Doan ,  Guy Blalock ,  Lyle Breiner ,  Er-Xuan Ping

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/84 ,  Y10S438/964

    摘要： The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.

    SEMICONDUCTOR STRUCTURES INCLUDING VERTICAL DIODE STRUCTURES AND METHODS OF MAKING THE SAME
    9.
    发明申请
    SEMICONDUCTOR STRUCTURES INCLUDING VERTICAL DIODE STRUCTURES AND METHODS OF MAKING THE SAME 失效
    包括垂直二极管结构的半导体结构及其制造方法

    公开(公告)号：US20080032480A1

    公开(公告)日：2008-02-07

    申请号：US11869012

    申请日：2007-10-09

    申请人： Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

    发明人： Fernando Gonzalez ,  Tyler Lowrey ,  Trung Doan ,  Raymond Turi ,  Graham Wolstenholme

    IPC分类号： H01L21/20 ,  H01L29/00

    CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/0814 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861 ,  H01L45/04 ,  H01L45/145 ,  Y10S257/903 ,  Y10S257/91 ,  Y10S438/979

    摘要： Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

    摘要翻译： 提供了制造垂直二极管结构的半导体结构和方法。 垂直二极管结构可以具有延伸穿过绝缘层并接触硅晶片上的有源区的二极管开口。 硅化钛层可以形成在二极管开口的内表面上并与活性区接触。 二极管开口最初可以填充非晶硅插塞，其在沉积期间被掺杂并随后重结晶以形成大晶粒多晶硅。 硅插头具有可以重掺杂第一类型掺杂剂的顶部部分和可以轻掺杂第二类型掺杂剂的底部部分。 顶部可以由底部限定，以便不与硅化钛层接触。 在垂直二极管结构的一个实施例中，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

    CONTROLLABLE OVONIC PHASE-CHANGE SEMICONDUCTOR MEMORY DEVICE AND METHODS OF PROGRAMMING THE SAME
    10.
    发明申请
    CONTROLLABLE OVONIC PHASE-CHANGE SEMICONDUCTOR MEMORY DEVICE AND METHODS OF PROGRAMMING THE SAME 有权
    可控的相位变化半导体存储器件及其编程方法

    公开(公告)号：US20080019167A1

    公开(公告)日：2008-01-24

    申请号：US11833034

    申请日：2007-08-02

    申请人： Trung Doan ,  D. Durcan ,  Brent Gilgen

    发明人： Trung Doan ,  D. Durcan ,  Brent Gilgen

    IPC分类号： G11C11/00 ,  H01L29/04

    CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

    摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

    摘要翻译： 公开了一种在硫族化物存储器的电极之间具有减小的接触面积的超声相变半导体存储器件及其编程方法。 这种存储器件包括包括非平行侧壁的下电极。 绝缘材料覆盖下电极，使得下电极的上表面露出。 在一个实施例中，绝缘材料和下电极可以具有共面上表面。 在另一个实施例中，下电极的上表面在绝缘材料的凹槽内。 硫族化物材料和上电极形成在下电极的上表面上。 这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。