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    BRAKE DEVICE ARRANGEMENT AND AUXILIARY DEVICE ARRANGEMENT OF A PNEUMATIC BRAKE SYSTEM OF A VEHICLE
    1.
    发明申请
    BRAKE DEVICE ARRANGEMENT AND AUXILIARY DEVICE ARRANGEMENT OF A PNEUMATIC BRAKE SYSTEM OF A VEHICLE 审中-公开
    汽车气动制动系统的制动装置装置和辅助装置装置

    公开(公告)号：US20110273004A1

    公开(公告)日：2011-11-10

    申请号：US13120216

    申请日：2009-09-23

    申请人： Hartmut Mann ,  Thomas Ernst ,  Jörg-Johannes Wach

    发明人： Hartmut Mann ,  Thomas Ernst ,  Jörg-Johannes Wach

    IPC分类号： B60T13/68 ,  B60T13/26 ,  B60T8/176 ,  B60T11/28

    CPC分类号： B60T17/04 ,  B60T13/26 ,  B60T13/683

    摘要： A brake device arrangement and auxiliary device arrangement of a pneumatic brake system of a vehicle include a pneumatic control valve and other pneumatic components for carrying out braking functions or auxiliary braking functions of the braking system. In order to produce a modular construction, a brake control module, which is pre-mounted on a support for producing a braking pressure, is arranged adjacent to a filter module, for treating the air on the input side, and at least one auxiliary module for fulfilling the auxiliary braking functions.

    摘要翻译： 车辆的气动制动系统的制动装置布置和辅助装置布置包括用于执行制动系统的制动功能或辅助制动功能的气动控制阀和其它气动部件。 为了制造模块化结构，预先安装在用于产生制动压力的支撑件上的制动控制模块邻近过滤器模块设置，用于处理输入侧的空气，以及至少一个辅助模块 用于实现辅助制动功能。

    MULTILEVEL MEMORY DEVICE
    2.
    发明申请
    MULTILEVEL MEMORY DEVICE 有权
    多媒体存储设备

    公开(公告)号：US20120134206A1

    公开(公告)日：2012-05-31

    申请号：US13304531

    申请日：2011-11-25

    申请人： Alexandre Hubert ,  Maryline Bawedin ,  Sorin Cristoloveanu ,  Thomas Ernst

    发明人： Alexandre Hubert ,  Maryline Bawedin ,  Sorin Cristoloveanu ,  Thomas Ernst

    IPC分类号： G11C11/34 ,  H01L29/792

    CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/0665 ,  H01L29/0673

    摘要： A memory device comprising: a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material capable of receiving electrons and holes, and able to perform storage of electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material capable of performing storage of electrical charges, a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.

    摘要翻译： 一种存储器件，包括：背栅，其包括导电材料的第一部分，布置在所述背栅上的介电材料的第一部分，布置在所述介电材料的第一部分上的半导体纳米结构体，覆盖所述半导体的介电材料的第二部分 nanobeam，能够接收电子和空穴的材料的一部分，并且能够执行电荷的存储并覆盖介电材料的第二部分;覆盖能够执行电荷存储的材料部分的介电材料的第三部分， 前门包括覆盖电介质材料的第三部分的导电材料的第二部分。

    STRUCTURE AND PRODUCTION PROCESS OF A MICROELECTRONIC 3D MEMORY DEVICE OF FLASH NAND TYPE
    4.
    发明申请
    STRUCTURE AND PRODUCTION PROCESS OF A MICROELECTRONIC 3D MEMORY DEVICE OF FLASH NAND TYPE 有权
    闪存NAND类型的微电子3D存储器件的结构和生产过程

    公开(公告)号：US20110169067A1

    公开(公告)日：2011-07-14

    申请号：US13003111

    申请日：2009-07-10

    申请人： Thomas Ernst ,  Gabriel Molas ,  Barbara De Salvo ,  Stephane Becu

    发明人： Thomas Ernst ,  Gabriel Molas ,  Barbara De Salvo ,  Stephane Becu

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/115 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203

    摘要： A microelectronic flash memory device including a plurality of memory cells including transistors fitted with a matrix of channels connecting a block of common source to a second block on which bit lines rest, the transistors also being formed by a plurality of gates including at least one gate material, including a first selection gate coating the channels, a plurality of control gates coating the channels, a plurality of second selection gates each coating the channels of the same row and the matricial arrangement, at least one or more of the gates based on superposition of layers including at least one first layer of dielectrical material, at least one charge store zone, and at least one second layer of dielectrical material.

    摘要翻译： 一种微电子闪速存储器件，包括多个存储器单元，其包括晶体管，该晶体管装配有将公共源的块连接到其上位于其上的第二块的通道矩阵，所述晶体管也由多个栅极形成，所述多个栅极包括至少一个栅极 材料，包括涂覆通道的第一选择栅极，涂覆通道的多个控制栅极，多个第二选择栅极，每个第二选择栅极覆盖相同行的沟道和基底布置，至少一个或多个栅极基于叠加 包括至少一个介电材料的第一层，至少一个电荷存储区和至少一个第二介电层。

    Method of fabricating a microelectronic structure of a semiconductor on insulator type with different patterns
    6.
    发明授权
    Method of fabricating a microelectronic structure of a semiconductor on insulator type with different patterns 有权
    制造具有不同图案的绝缘体半导体微电子结构的方法

    公开(公告)号：US07879690B2

    公开(公告)日：2011-02-01

    申请号：US12413130

    申请日：2009-03-27

    申请人： Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

    发明人： Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

    IPC分类号： H01L21/30 ,  H01L21/46

    CPC分类号： H01L21/76254

    摘要： A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.

    摘要翻译： 通过形成包括形成衬底的板，连续绝缘层和半导体层的层叠均匀结构，来产生具有不同图案的绝缘体半导体型微结构。 连续绝缘层是至少三个基本层的堆叠，包括底部基本层，至少一个中间基本层和覆盖半导体层的顶部基本层，其中底部基本层和顶部基本层中的至少一个 层是绝缘材料。 在层叠的均匀结构中，通过修改其中一个图案中的至少一个基本层来区分至少两个图案，使得元件层在两个图案之间具有显着不同的物理或化学性质，其中至少一个 底部和顶部基本层是保持不变的绝缘材料。

    Multilevel memory device
    7.
    发明授权
    Multilevel memory device 有权
    多级存储器件

    公开(公告)号：US09019760B2

    公开(公告)日：2015-04-28

    申请号：US13304531

    申请日：2011-11-25

    申请人： Alexandre Hubert ,  Maryline Bawedin ,  Sorin Cristoloveanu ,  Thomas Ernst

    发明人： Alexandre Hubert ,  Maryline Bawedin ,  Sorin Cristoloveanu ,  Thomas Ernst

    IPC分类号： G11C11/40 ,  H01L27/108 ,  H01L29/792 ,  B82Y10/00 ,  H01L21/28 ,  H01L27/115 ,  H01L29/06

    CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/0665 ,  H01L29/0673

    摘要： A memory device is provided, including a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material configured to receive electrons and holes, and configured to store electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material configured to perform storage of electrical charges, and a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.

    摘要翻译： 提供了一种存储器件，包括一个包括导电材料的第一部分的背栅，布置在背栅上的介质材料的第一部分，布置在电介质材料第一部分上的半导体纳米结构体，覆盖电介质材料的第二部分 半导体纳米结构体，被配置为接收电子和空穴并被配置为存储电荷并覆盖电介质材料的第二部分的材料的一部分，覆盖被配置为执行电荷存储的材料部分的介电材料的第三部分，以及 前门，其包括覆盖电介质材料的第三部分的导电材料的第二部分。

    SRAM memory cell provided with transistors having a vertical multichannel structure
    9.
    发明授权
    SRAM memory cell provided with transistors having a vertical multichannel structure 有权
    具有垂直多通道结构的晶体管的SRAM存储单元

    公开(公告)号：US08502318B2

    公开(公告)日：2013-08-06

    申请号：US12740907

    申请日：2008-11-07

    申请人： Olivier Thomas ,  Thomas Ernst

    发明人： Olivier Thomas ,  Thomas Ernst

    IPC分类号： H01L29/66

    CPC分类号： G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/78696

    摘要： A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k≧1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.

    摘要翻译： 一种微电子器件，在衬底上包括诸如SRAM存储单元的至少一个元件; 分别包括在与衬底的主平面形成非零角度的方向上平行的数k个通道（k> = 1）的一个或多个第一晶体管和一个或多个第二晶体管， 分别包括与形成非零角度的方向或正交方向平行的m> k个通道的数量m与基板的主平面。

    Method of manufacturing nanowires parallel to the supporting substrate
    10.
    发明授权
    Method of manufacturing nanowires parallel to the supporting substrate 有权
    制造平行于支撑衬底的纳米线的方法

    公开(公告)号：US08252636B2

    公开(公告)日：2012-08-28

    申请号：US12267431

    申请日：2008-11-07

    申请人： Erwan Dornel ,  Jean-Charles Barbe ,  Thomas Ernst

    发明人： Erwan Dornel ,  Jean-Charles Barbe ,  Thomas Ernst

    IPC分类号： H01L21/335 ,  H01L21/8232 ,  H01L29/775

    CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/7613 ,  H01L29/775 ,  H01L29/78645 ,  H01L29/78696

    摘要： A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method including the formation on the supporting substrate of a structure comprising a bar and two regions, a first end of the bar being secured to one of the two regions and a second end of the bar being secured to the other region, the width of the bar being less than the width of the regions, the subjection of the bar to an annealing under gaseous atmosphere in order to transform the bar into a nanowire, the annealing being carried out under conditions allowing control of the sizing of the neck produced during the formation of the nanowire.

    摘要翻译： 一种制造至少一个纳米线的方法，所述纳米线平行于其支撑衬底，所述方法包括在支撑衬底上形成包括棒和两个区域的结构，所述棒的第一端固定到两个之一 区域，并且杆的第二端固定到另一区域，杆的宽度小于区域的宽度，在棒状气体气氛下退火以便将棒转变成纳米线， 退火在允许控制在纳米线形成期间产生的颈部上浆的条件下进行。