公开(公告)号：US07078800B2

公开(公告)日：2006-07-18

申请号：US10957176

申请日：2004-09-30

申请人： Heung-Kyu Kwon ,  Se-Yong Oh ,  Min-Ha Kim ,  Tae-Je Cho

发明人： Heung-Kyu Kwon ,  Se-Yong Oh ,  Min-Ha Kim ,  Tae-Je Cho

IPC分类号： H01L23/12

CPC分类号： H01L23/433 ,  H01L23/36 ,  H01L23/4334 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/00

摘要： Semiconductor packages are provided to prevent a chip, such as a central processing unit (CPU) chip, from being degraded due to hot spot heat generated during the operation of the chip and absorbs thermomechanical stresses in interfaces between the chip, a thermal interface material (TIM) and a lid. The chip is electrically connected, e.g., flip-chip bonded, to a package substrate. The lid is thermally connected to and disposed over a back surface of the chip with the TIM interposed therebetween. A heat dissipation means adjacent the TIM is also located between the lid and the chip to prevent the hot spot effect.

公开(公告)号：US06952050B2

公开(公告)日：2005-10-04

申请号：US10245228

申请日：2002-09-16

申请人： Heung-Kyu Kwon ,  Se-Yong Oh ,  Min-Ha Kim ,  Tae-Je Cho

发明人： Heung-Kyu Kwon ,  Se-Yong Oh ,  Min-Ha Kim ,  Tae-Je Cho

IPC分类号： H01L23/34 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H01L23/12

CPC分类号： H01L23/433 ,  H01L23/36 ,  H01L23/4334 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/00

摘要： Semiconductor packages are provided to prevent a chip, such as a central processing unit (CPU) chip, from being degraded due to hot spot heat generated during the operation of the chip and absorbs thermomechanical stresses in interfaces between the chip, a thermal interface material (TIM) and a lid. The chip is electrically connected, e.g., flip-chip bonded, to a package substrate. The lid is thermally connected to and disposed over a back surface of the chip with the TIM interposed therebetween. A heat dissipation means adjacent the TIM is also located between the lid and the chip to prevent the hot spot effect.

公开(公告)号：US20050056928A1

公开(公告)日：2005-03-17

申请号：US10957176

申请日：2004-09-30

申请人： Heung-Kyu Kwon ,  Se-Yong Oh ,  Min-Ha Kim ,  Tae-Je Cho

发明人： Heung-Kyu Kwon ,  Se-Yong Oh ,  Min-Ha Kim ,  Tae-Je Cho

IPC分类号： H01L23/34 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H01L23/12

CPC分类号： H01L23/433 ,  H01L23/36 ,  H01L23/4334 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/00

摘要： Semiconductor packages are provided to prevent a chip, such as a central processing unit (CPU) chip, from being degraded due to hot spot heat generated during the operation of the chip and absorbs thermomechanical stresses in interfaces between the chip, a thermal interface material (TIM) and a lid. The chip is electrically connected, e.g., flip-chip bonded, to a package substrate. The lid is thermally connected to and disposed over a back surface of the chip with the TIM interposed therebetween. A heat dissipation means adjacent the TIM is also located between the lid and the chip to prevent the hot spot effect.

摘要翻译： 提供半导体封装以防止诸如中央处理单元（CPU）芯片的芯片由于在芯片的操作期间产生的热点热而劣化，并且吸收芯片，热界面材料之间的界面中的热机械应力 TIM）和盖子。 该芯片与封装衬底电连接，例如倒装芯片接合。 盖子被热连接到芯片的后表面并且设置在芯片的后表面上，其中TIM插入其间。 靠近TIM的散热装置也位于盖和芯片之间，以防止热点效应。

公开(公告)号：US07812442B2

公开(公告)日：2010-10-12

申请号：US11778536

申请日：2007-07-16

申请人： Heung-Kyu Kwon ,  Tae-Je Cho ,  Min-Ha Kim

发明人： Heung-Kyu Kwon ,  Tae-Je Cho ,  Min-Ha Kim

IPC分类号： H05K7/20 ,  H01L23/10

CPC分类号： H01L23/3128 ,  H01L23/24 ,  H01L23/36 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  Y10T29/49156 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012

摘要： Provided are a high-power ball grid array (BGA) and a method for manufacturing the high-power BGA. The high-power BGA includes a printed circuit board which has a through hole at its center, connection pads which are formed on the bottom of the printed circuit board, matrix solder balls which surround the through hole and are adjacent to the connection pads on the bottom of the printed circuit board, a heat spreader which is formed on the top surface of the printed circuit board and includes an insulating layer of a high thermal conductivity, a semiconductor chip which is mounted downwardly on the bottom surface of the heat spreader, within the through hole, and includes a plurality of pads for bonding via gold wires with the connection pad, and a passive film which fills the through hole and is formed at the bottom of the semiconductor chip. By interposing a ceramic between the semiconductor chip and the heat spreader, for insulating, the generation of charges between the semiconductor chip and the heat spreader can be sharply reduced, and defects such as ESD (electrostatic discharge) can be reduced when testing for the ESD and mounting the package.

摘要翻译： 提供了大功率球栅阵列（BGA）和制造大功率BGA的方法。 大功率BGA包括在其中心具有通孔的印刷电路板，形成在印刷电路板的底部的连接焊盘，围绕通孔并且邻近印刷电路板上的连接焊盘的矩阵焊球 印刷电路板的底部，散热器，其形成在印刷电路板的顶表面上，并且包括高导热性的绝缘层，在散热器的底面上向下安装的半导体芯片， 通孔，并且包括用于通过金线与连接焊盘接合的多个焊盘，以及填充通孔并形成在半导体芯片的底部的钝化膜。 通过在半导体芯片和散热器之间插入陶瓷以进行绝缘，可以大大降低半导体芯片和散热器之间的电荷的产生，并且在测试ESD时可以减少ESD（静电放电）等缺点 并安装包装。

公开(公告)号：US07258808B2

公开(公告)日：2007-08-21

申请号：US10459400

申请日：2003-06-10

申请人： Heung-Kyu Kwon ,  Tae-Je Cho ,  Min-Ha Kim

发明人： Heung-Kyu Kwon ,  Tae-Je Cho ,  Min-Ha Kim

IPC分类号： H01L21/00 ,  H05K3/02

CPC分类号： H01L23/3128 ,  H01L23/24 ,  H01L23/36 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  Y10T29/49156 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012

摘要： A high-power BGA includes a printed circuit board with a through hole, connection pads formed on the bottom of the printed circuit board, matrix solder balls surrounding the through hole and adjacent to the connection pads, a heat spreader on the top surface of the printed circuit board that includes an insulating layer of a high thermal conductivity, a semiconductor chip mounted within the through hole on the bottom surface of the heat spreader that includes a number of contact pads for bonding with the connection pads using gold wires, and a passive film filling the through hole and around the semiconductor chip. By interposing a ceramic insulating layer between the semiconductor chip and the heat spreader, charge generation between the semiconductor chip and the heat spreader is sharply reduced, and defects such as ESD (electrostatic discharge) is reduced during testing and mounting of the package.

摘要翻译： 大功率BGA包括具有通孔的印刷电路板，形成在印刷电路板底部的连接焊盘，围绕通孔并与连接焊盘相邻的基体焊球，在该顶部表面上的散热器 印刷电路板，其包括高导热性的绝缘层，安装在散热器底表面上的通孔内的半导体芯片，其包括用于使用金线与连接焊盘接合的多个接触焊盘，以及被动 胶片填充通孔和半导体芯片周围。 通过在半导体芯片和散热器之间插入陶瓷绝缘层，半导体芯片和散热器之间的电荷产生急剧减少，并且在封装的测试和安装期间诸如ESD（静电放电）的缺陷减少。

公开(公告)号：US07327038B2

公开(公告)日：2008-02-05

申请号：US11322886

申请日：2005-12-27

申请人： Heung-Kyu Kwon ,  Tae-Je Cho ,  Kyung-Lae Jang

发明人： Heung-Kyu Kwon ,  Tae-Je Cho ,  Kyung-Lae Jang

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/49 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Provided is a semiconductor device package in which instability of a bonding wire that may occur when a plurality of semiconductor chips are stacked is prevented and which obtains a light, thin and small structure. The semiconductor device package includes a substrate having a plurality of substrate pads on a top surface of the semiconductor device package and includes a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips have a chip pad electrically connected to a common pin, e.g., to which a common signal may be concurrently applied to each of the semiconductor chips. An interposer chip, also stacked on the substrate, has a connecting wire electrically connected to the chip pad, the common pin of each of the semiconductor chips being thereby electrically coupled at the connecting wire via the chip pad, and the connecting wire being thereby electrically connected to the substrate pad.

摘要翻译： 提供一种半导体器件封装，其中防止了当堆叠多个半导体芯片时可能发生的接合线的不稳定性，并获得轻薄的结构。 半导体器件封装包括在半导体器件封装的顶表面上具有多个衬底焊盘并且包括堆叠在衬底上的多个半导体芯片的衬底。 每个半导体芯片具有电连接到公共引脚的芯片焊盘，例如可以将公共信号同时施加到每个半导体芯片。 也堆叠在基板上的插入式芯片具有电连接到芯片焊盘的连接线，因此每个半导体芯片的公共引脚通过芯片焊盘在连接线处电耦合，并且连接线由此电连接 连接到基板垫。

公开(公告)号：US20060138624A1

公开(公告)日：2006-06-29

申请号：US11322886

申请日：2005-12-27

申请人： Heung-Kyu Kwon ,  Tae-Je Cho ,  Kyung-Lae Jang

发明人： Heung-Kyu Kwon ,  Tae-Je Cho ,  Kyung-Lae Jang

IPC分类号： H01L23/02

CPC分类号： H01L24/49 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Provided is a semiconductor device package in which instability of a bonding wire that may occur when a plurality of semiconductor chips are stacked is prevented and which obtains a light, thin and small structure. The semiconductor device package includes a substrate having a plurality of substrate pads on a top surface of the semiconductor device package and includes a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips have a chip pad electrically connected to a common pin, e.g., to which a common signal may be concurrently applied to each of the semiconductor chips. An interposer chip, also stacked on the substrate, has a connecting wire electrically connected to the chip pad, the common pin of each of the semiconductor chips being thereby electrically coupled at the connecting wire via the chip pad, and the connecting wire being thereby electrically connected to the substrate pad.

摘要翻译： 提供一种半导体器件封装，其中防止了当堆叠多个半导体芯片时可能发生的接合线的不稳定性，并获得轻薄的结构。 半导体器件封装包括在半导体器件封装的顶表面上具有多个衬底焊盘并且包括堆叠在衬底上的多个半导体芯片的衬底。 每个半导体芯片具有电连接到公共引脚的芯片焊盘，例如可以将公共信号同时施加到每个半导体芯片。 也堆叠在基板上的插入式芯片具有电连接到芯片焊盘的连接线，因此每个半导体芯片的公共引脚通过芯片焊盘在连接线处电耦合，并且连接线由此电连接 连接到基板垫。

公开(公告)号：US08902356B2

公开(公告)日：2014-12-02

申请号：US13049767

申请日：2011-03-16

申请人： Byoung-Rim Seo ,  Beoung-Ouk Min ,  Tae-Je Cho ,  Yung-Cheol Kong ,  Dong-Min Kim ,  Ji-Woong Park

发明人： Byoung-Rim Seo ,  Beoung-Ouk Min ,  Tae-Je Cho ,  Yung-Cheol Kong ,  Dong-Min Kim ,  Ji-Woong Park

IPC分类号： H04N5/225 ,  H01L27/146

CPC分类号： H01L27/14618 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： An image sensor module includes a circuit board, an image sensor package and an optical system. The circuit board has an upper surface and a lower surface, the substrate having a window. The image sensor package includes a mounting substrate and an image sensor chip mounted on the mounting substrate, the image sensor package being adhered to the lower surface of the circuit board such that the image sensor chip is exposed through the window. The optical system is provided on the upper surface of the circuit board to guide light from an object to the image sensor chip.

摘要翻译： 图像传感器模块包括电路板，图像传感器封装和光学系统。 电路板具有上表面和下表面，基板具有窗口。 图像传感器封装包括安装基板和安装在安装基板上的图像传感器芯片，图像传感器封装被粘附到电路板的下表面，使得图像传感器芯片通过窗口露出。 光学系统设置在电路板的上表面上以将来自物体的光引导到图像传感器芯片。

公开(公告)号：US07928435B2

公开(公告)日：2011-04-19

申请号：US12453144

申请日：2009-04-30

申请人： Sung-Yong Park ,  Tae-Je Cho ,  Tae-Hun Kim ,  Jong-Kook Kim ,  Byeong-Yeon Cho

发明人： Sung-Yong Park ,  Tae-Je Cho ,  Tae-Hun Kim ,  Jong-Kook Kim ,  Byeong-Yeon Cho

IPC分类号： H01L23/58

CPC分类号： H01L25/0657 ,  G01R31/31723 ,  G01R31/31813 ,  H01L22/32 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An interposer chip may include an insulating substrate, conductive patterns, and a test pattern. The conductive patterns may be formed on the insulating substrate. Further, the conductive patterns may be electrically connected to conductive wires. The test pattern may be connected to the conductive patterns. A test current for testing an electrical connection between the conductive patterns and the conductive wires may flow through the test pattern. Thus, the interposer chip may have the test pattern connected to the conductive patterns, so that the test current may flow to the test pattern through the conductive wires and the conductive patterns. As a result, an electrical connection between the conductive wires and the conductive patterns may be identified based on the test current supplied to the test pattern.

摘要翻译： 插入器芯片可以包括绝缘基板，导电图案和测试图案。 导电图案可以形成在绝缘基板上。 此外，导电图案可以电连接到导电线。 测试图案可以连接到导电图案。 用于测试导电图案和导线之间的电连接的测试电流可以流过测试图案。 因此，插入器芯片可以具有连接到导电图案的测试图案，使得测试电流可以通过导线和导电图案流到测试图案。 结果，可以基于提供给测试图案的测试电流来识别导线和导电图案之间的电连接。

公开(公告)号：US07884392B2

公开(公告)日：2011-02-08

申请号：US12362210

申请日：2009-01-29

申请人： Hyuek-Jae Lee ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

发明人： Hyuek-Jae Lee ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

IPC分类号： H01L31/0328

CPC分类号： H01L27/14623 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05099

摘要： One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the photoelectric converting portion; an external connection terminal on the rear surface of the substrate, wherein the external connection terminal is connected to the through via; and a light shading layer formed on a portion of the rear surface of the substrate, wherein the light shading layer is substantially opaque with respect to an external light. In some embodiments, the portion of the rear surface of the substrate on which the light shading layer is formed is not overlapped by the through via or the external connection terminal.

摘要翻译： 本文示例性描述的一个实施例可以被表征为包括具有前表面和后表面的基板的图像传感器; 在所述基板的前表面上的光电转换部; 贯穿所述基板延伸的通孔，其中所述通孔电连接到所述光电转换部分; 在所述基板的后表面上的外部连接端子，其中所述外部连接端子连接到所述通孔; 以及形成在所述基板的后表面的一部分上的遮光层，其中所述遮光层相对于外部光基本上是不透明的。 在一些实施例中，其上形成有遮光层的基板的后表面的部分不与通孔或外部连接端子重叠。