公开(公告)号：US07323769B2

公开(公告)日：2008-01-29

申请号：US11429248

申请日：2006-05-08

申请人： Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Francis Koon Seong Poh

发明人： Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Francis Koon Seong Poh

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip. Each of the wires has a first end electrically conductively joined to the first face of the integrated circuit chip. The first end of the wire, therefore, is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the integrated circuit chip. Each of the wires also has a second end electrically conductively joined to the first face of one of the leads. The second end of the wire, therefore, is disposed between a plane defined by a first face of the die pad and a plane defined by the first face of the lead to which it is joined.

摘要翻译： 公开了一种集成电路封装。 该包装包括多个引线，每个引线具有第一面和与该第一面相对的第二面。 封装还包括具有第一面和与第一面相对的第二面的管芯焊盘。 管芯焊盘的第二面与引线的第二面正交地偏移，使得管芯焊盘的第二面和引线的第二面不共面。 封装还包括基本上横向设置在多个引线之间的集成电路芯片，并且具有与第一面相对的第一面和第二面。 集成电路芯片的第一面靠近芯片焊盘的第二面，并且集成电路芯片的第一面耦合到管芯焊盘的第二面。 封装还包括将多个引线连接到集成电路芯片的多个导线。 每根导线具有导电地连接到集成电路芯片的第一面的第一端。 因此，线的第一端设置在由芯片焊盘的第二面限定的平面和由集成电路芯片的第一面限定的平面之间。 每个电线还具有导电地连接到一个引线的第一面的第二端。 因此，线的第二端设置在由芯片焊盘的第一面限定的平面和由其连接的引线的第一面限定的平面之间。

公开(公告)号：US20060192292A1

公开(公告)日：2006-08-31

申请号：US11260091

申请日：2005-10-28

申请人： Chuen Khiang Wang ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Sin Nee Song ,  Steven Yu Yao ,  Hua Hong Tan

发明人： Chuen Khiang Wang ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Sin Nee Song ,  Steven Yu Yao ,  Hua Hong Tan

IPC分类号： H01L23/52

CPC分类号： H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.

摘要翻译： 一种半导体芯片封装及其制造方法。 第一芯片单元包括电连接到第一基板的第一基板和第一IC芯片。 第二芯片单元包括电子连接到第二基板的第二基板和第二IC芯片。 粘合材料设置在第一IC芯片的表面上，第二芯片单元安装在包括粘合材料的第一芯片单元的表面上，使得第二结构的至少一部分被粘合材料封装，从而 在与安装相同的步骤中提供一些封装。 第一芯片单元和第二芯片单元可以由也可以提供电连接的间隔件分开。

公开(公告)号：US07816775B2

公开(公告)日：2010-10-19

申请号：US11662431

申请日：2005-09-09

申请人： Chuen Khiang Wang ,  Hao Liu ,  Hien Boon Tan ,  Clifton Teik Lyk Law ,  Rahamat Bidin ,  Anthony Yi Sheng Sun

发明人： Chuen Khiang Wang ,  Hao Liu ,  Hien Boon Tan ,  Clifton Teik Lyk Law ,  Rahamat Bidin ,  Anthony Yi Sheng Sun

IPC分类号： H01L23/02

CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of leads of a leadframe, and an adhesive is applied onto the set of leads at a second side opposite to the first side. A second die is attached onto the adhesive. The adhesive fills into the gaps defined by the set of leads. The adhesive is thereafter cured. In a multi-chip integrated circuit package made according to the method, the adhesive attaching the second die fills the gaps between the leads so that to avoid formation of internal cavities of the package.

摘要翻译： 公开了一种用于制造集成电路封装的方法和一种多芯片集成电路封装。 根据该方法，将第一管芯附接到引线框架的一组引线的第一侧上，并且在与第一侧相对的第二侧将粘合剂施加到引线组上。 第二个模具附着在粘合剂上。 粘合剂填充到由一组引线限定的间隙中。 之后固化粘合剂。 在根据该方法制造的多芯片集成电路封装中，附着第二模具的粘合剂填充引线之间的间隙，从而避免形成封装的内部空腔。

公开(公告)号：US07375416B2

公开(公告)日：2008-05-20

申请号：US11406357

申请日：2006-04-19

申请人： Danny Vallejo Retuta ,  Hien Boon Tan ,  Susanto Tanary ,  Anthony Yi Sheng Sun ,  Soon Huat James Tan

发明人： Danny Vallejo Retuta ,  Hien Boon Tan ,  Susanto Tanary ,  Anthony Yi Sheng Sun ,  Soon Huat James Tan

IPC分类号： H01L23/48

CPC分类号： H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.

摘要翻译： 半导体封装包括多个第一引线，每个第一引线具有从引线除去的顶部外部部分和外端，以及多个第二引线，每个引线具有从引线除去的底部外部部分和外部端部。 第一和第二引线沿着封装的边缘彼此交替。 此外，第一引线的外端沿着封装的边缘形成第一排，并且第二引线的外端沿着封装的边缘形成第二排。 在一个实施例中，第一和第二行彼此平行，并且密封剂覆盖第一和第二引线的至少一部分。

公开(公告)号：US08030768B2

公开(公告)日：2011-10-04

申请号：US12108563

申请日：2008-04-24

申请人： Roel Robles ,  Danny Retuta ,  Mary Annie Cheong ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Richard Gan

发明人： Roel Robles ,  Danny Retuta ,  Mary Annie Cheong ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Richard Gan

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L24/16 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/12 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections.

摘要翻译： 一种半导体封装，其具有在第一表面上具有凹凸金属化（UBM）的半导体芯片和具有开放通孔的基板。 衬底被附接到半导体芯片，UBM与开放的通孔对准。 密封剂围绕半导体芯片和衬底，并且导体填充开放通孔以形成外部封装连接。

公开(公告)号：US07678610B2

公开(公告)日：2010-03-16

申请号：US11260091

申请日：2005-10-28

申请人： Chuen Khiang Wang ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Sin Nee Song ,  Steven Yu Feng Yao ,  Hua Hong Tan

发明人： Chuen Khiang Wang ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Sin Nee Song ,  Steven Yu Feng Yao ,  Hua Hong Tan

IPC分类号： H01L21/00

CPC分类号： H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.

摘要翻译： 一种半导体芯片封装及其制造方法。 第一芯片单元包括电连接到第一基板的第一基板和第一IC芯片。 第二芯片单元包括电子连接到第二基板的第二基板和第二IC芯片。 粘合材料设置在第一IC芯片的表面上，第二芯片单元安装在包括粘合材料的第一芯片单元的表面上，使得第二结构的至少一部分被粘合材料封装，从而 在与安装相同的步骤中提供一些封装。 第一芯片单元和第二芯片单元可以由也可以提供电连接的间隔件分开。

公开(公告)号：US20080290509A1

公开(公告)日：2008-11-27

申请号：US10581395

申请日：2004-12-02

申请人： Hien Boon Tan ,  Chuen Khiang Wang ,  Rahamat Bidin ,  Anthony Yi Sheng Sun ,  Desmond Yok Rue Chong ,  Ravi Kanth Kolan

发明人： Hien Boon Tan ,  Chuen Khiang Wang ,  Rahamat Bidin ,  Anthony Yi Sheng Sun ,  Desmond Yok Rue Chong ,  Ravi Kanth Kolan

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L23/3114 ,  H01L21/76897 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/8191 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/81805

摘要： A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.

摘要翻译： 公开了一种制造芯片级封装的方法。 该方法包括将晶片切割成多个芯片阵列，每个阵列包括两个或多个集成电路芯片。 该方法还包括将每个阵列安装在基板上并将附接到基板的每个阵列切割成单独的芯片级封装，每个单独的芯片级封装仅包括一个集成电路芯片。

公开(公告)号：US09281218B2

公开(公告)日：2016-03-08

申请号：US11846658

申请日：2007-08-29

申请人： Danny Retuta ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Mary Annie Cheong

发明人： Danny Retuta ,  Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Mary Annie Cheong

IPC分类号： H01L21/00 ,  H01L21/48 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49506 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/495 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. Then, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.

摘要翻译： 制造引线框架的方法包括提供在顶表面具有多个孔的导电层。 多个孔在导电层上形成引线和管芯焊盘的结构。 多个孔填充有非导电材料。 下一个; 导电箔附着在导电层和非导电环氧材料的顶表面上。 然后，对导电箔进行蚀刻以形成引线，管芯焊盘，总线，坝条和连接线的网络，其中总线将引线连接到堤坝，坝条连接到连接线， 连接线连接到管芯焊盘。

公开(公告)号：US08129222B2

公开(公告)日：2012-03-06

申请号：US10721382

申请日：2003-11-26

申请人： Hien Boon Tan ,  Anthony Yi Sheng Sun

发明人： Hien Boon Tan ,  Anthony Yi Sheng Sun

IPC分类号： H01L21/00

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49527 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/50 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01079 ,  H01L2924/01202 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

摘要翻译： 一种集成电路封装，具有具有第一面和第二面的管芯焊盘，多个内部引线以及位于第一面和第二面之间的多个侧面。 多个内部引线被设置为与基板相配合并且基本上围绕芯片焊盘。 所述封装还包括多个外引线，所述多个外引线与所述多个内引线和所述管芯焊盘基本共面并且基本上围绕所述多个内引线和所述管芯焊盘设置，使得所述多个外引线中的每一个的侧面偏离所述多个引线 的内线。 设置在管芯焊盘的第一面上的第一粘合剂层和设置在多个内引线中的每一个的第一面上的第二粘合剂层。 IC芯片通过第一粘合层和穿过第二粘合剂层的多个内引线耦合到管芯焊盘的第一面。 该封装还包括将内引线和外引线连接到IC芯片的线。

公开(公告)号：US07476569B2

公开(公告)日：2009-01-13

申请号：US12113968

申请日：2008-05-02

申请人： Danny Vallejo Retuta ,  Hien Boon Tan ,  Susanto Tanary ,  Anthony Yi Sheng Sun ,  Soon Huat James Tan

发明人： Danny Vallejo Retuta ,  Hien Boon Tan ,  Susanto Tanary ,  Anthony Yi Sheng Sun ,  Soon Huat James Tan

IPC分类号： H01L23/48

CPC分类号： H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.

摘要翻译： 半导体封装包括多个第一引线，每个第一引线具有从引线除去的顶部外部部分和外端，以及多个第二引线，每个引线具有从引线除去的底部外部部分和外部端部。 第一和第二引线沿着封装的边缘彼此交替。 此外，第一引线的外端沿着封装的边缘形成第一排，并且第二引线的外端沿着封装的边缘形成第二排。 在一个实施例中，第一和第二行彼此平行，并且密封剂覆盖第一和第二引线的至少一部分。