公开(公告)号：US20080128851A1

公开(公告)日：2008-06-05

申请号：US11662285

申请日：2005-09-09

申请人： Hiroji Aga ,  Norihiro Kobayashi ,  Masayuki Imai ,  Tatsuo Enomoto ,  Hiroshi Takeno

发明人： Hiroji Aga ,  Norihiro Kobayashi ,  Masayuki Imai ,  Tatsuo Enomoto ,  Hiroshi Takeno

IPC分类号： H01L29/00 ,  H01L21/30

CPC分类号： H01L21/76254 ,  H01L21/3226

摘要： A method of manufacturing an SOI wafer includes a bonding step, a thinning and a bonding annealing step. Assuming refractive index n1 of SiO2 as 1.5, refractive index n2 of Si as 3.5, and optical thickness tOP of the silicon oxide film 2 and the SOI layer 15 in the infrared wavelength region as tOP=n1×t1+n2×t2, the thickness t1 of the silicon oxide film 2 and thickness t2 of the SOI layer so as to satisfy a relation of 0.1λ

摘要翻译： 一种制造SOI晶片的方法包括接合步骤，薄化和接合退火步骤。 假设SiO 2的折射率n 1为1.5，Si的折射率n 2为3.5，氧化硅膜2和SOI层15的光学厚度t OP 在红外波长区域中，作为t OP = N 1×t 1 + n 2×t 2，氧化硅膜2的厚度t 1和SOI层的厚度t 2满足关系 并且使得（t 1×n 1）/（t 2×n 2）落在0.2-3范围内。通过在键合退火之前进行的核激光退火 在接合退火之后将基底晶片中的氧沉淀形成密度调节到小于1×10 9 / cm 3以上。 该结构成功地提供了制造具有薄氧化硅膜和SOI层的SOI晶片的方法，并且不太可能引起翘曲。

公开(公告)号：US07902042B2

公开(公告)日：2011-03-08

申请号：US11662285

申请日：2005-09-09

申请人： Hiroji Aga ,  Norihiro Kobayashi ,  Masayuki Imai ,  Tatsuo Enomoto ,  Hiroshi Takeno

发明人： Hiroji Aga ,  Norihiro Kobayashi ,  Masayuki Imai ,  Tatsuo Enomoto ,  Hiroshi Takeno

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76254 ,  H01L21/3226

摘要： A method of manufacturing an SOI wafer includes a bonding step, a thinning and a bonding annealing step. Assuming refractive index n1 of SiO2 as 1.5, refractive index n2 of Si as 3.5, and optical thickness tOP of the silicon oxide film 2 and the SOI layer 15 in the infrared wavelength region as tOP=n1×t1+n2×t2, the thickness t1 of the silicon oxide film 2 and thickness t2 of the SOI layer so as to satisfy a relation of 0.1λ

摘要翻译： 一种制造SOI晶片的方法包括接合步骤，薄化和接合退火步骤。 假设SiO 2的折射率n1为1.5，Si的折射率n2为3.5，红外波长区域中的氧化硅膜2和SOI层15的光学厚度tOP为tOP = n1×t1 + n2×t2，厚度 氧化硅膜2的t1和SOI层的厚度t2以满足0.1λ

公开(公告)号：US07189293B2

公开(公告)日：2007-03-13

申请号：US10482099

申请日：2002-06-25

申请人： Norihiro Kobayashi ,  Masaro Tamatsuka ,  Takatoshi Nagoya ,  Wei Feig Qu ,  Hiroshi Takeno ,  Ken Aihara

发明人： Norihiro Kobayashi ,  Masaro Tamatsuka ,  Takatoshi Nagoya ,  Wei Feig Qu ,  Hiroshi Takeno ,  Ken Aihara

IPC分类号： C30B33/02

CPC分类号： H01L21/324 ,  C30B29/06 ,  C30B33/00 ,  H01L21/3225

摘要： The present invention is a method of producing an annealed wafer wherein a silicon single crystal wafer having a diameter of 200 mm or more produced by the Czochralski (CZ) method is subjected to a high temperature heat treatment in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes, and before the high temperature heat treatmen, a pre-annealing is performed at a temperature less than the temperature of the high temperature heat treatment, so that the growth of slip dislocations is suppressed by growing oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein the generation and growth of slip dislocations generated in a high temperature heat treatment are suppressed and the defect density in the wafer surface layer is lowered even in the case of a silicon single crystal wafer having a large diameter of 200 mm or more, and the annealed wafer.

摘要翻译： 本发明是一种退火晶片的制造方法，其中通过Czochralski（CZ）方法制造的直径为200mm以上的硅单晶晶片在氩气气氛中进行高温热处理， 氢气或其混合气体在1100-1350℃的温度下进行10-600分钟，在高温热处理之前，在低于高温热的温度下进行预退火 从而通过生长氧化物沉淀物来抑制滑移位错的生长。 因此，提供了一种制造退火晶片的方法，其中抑制了在高温热处理中产生的滑移位错的产生和生长，并且即使在硅单晶晶片的情况下晶片表面层中的缺陷密度也降低 具有大直径为200mm以上的退火晶片。

公开(公告)号：US06544899B2

公开(公告)日：2003-04-08

申请号：US10019298

申请日：2002-01-04

申请人： Hiroshi Takeno ,  Norihiro Kobayashi

发明人： Hiroshi Takeno ,  Norihiro Kobayashi

IPC分类号： H01L21469

CPC分类号： H01L21/3225

摘要： There is provided a process for manufacturing a silicon epitaxial wafer capable of manufacturing an epitaxial wafer, which exerts a stable IG capability without being affected by a thermal history of a substrate for epitaxial growth and has the IG capability excellent from an early stage of a device process, and particularly, canceling an IG shortage in an N/N+ epitaxial wafer caused by a problem that oxygen precipitation is hard to proceed in an N+ substrate with a simple and easy way. RTA (rapid heating and rapid cooling heat treatment) is performed at a temperature of 1200° C. to 1350° C. for 1 to 120 seconds on a silicon substrate for epitaxial growth; further heat treatment is performed at a temperature of 900° C. to 1050° C. for 2 to 20 hours on the silicon substrate for epitaxial growth; and thereafter, an epitaxial layer is formed on a surface of the silicon substrate.

摘要翻译： 提供了一种制造能够制造外延晶片的硅外延晶片的方法，该外延晶片发挥稳定的IG能力，而不受用于外延生长的衬底的热历史的影响，并且具有从器件的早期阶段优异的IG能力 特别是通过简单且容易的方式，在N +衬底中难以进行氧析出的问题，来消除N / N +外延晶片中的IG短路。 在1200℃至1350℃的温度下，在用于外延生长的硅基板上进行1〜120秒的RTA（快速加热和快速冷却热处理） 在硅衬底上在900℃至1050℃的温度下进行进一步的热处理2至20小时，用于外延生长; 之后，在硅衬底的表面上形成外延层。

公开(公告)号：US08410573B2

公开(公告)日：2013-04-02

申请号：US12734240

申请日：2008-10-20

申请人： Hiroshi Ohtsuki ,  Mitsutaka Katada ,  Nobuhiko Noto ,  Hiroshi Takeno ,  Kazuhiko Yoshida

发明人： Hiroshi Ohtsuki ,  Mitsutaka Katada ,  Nobuhiko Noto ,  Hiroshi Takeno ,  Kazuhiko Yoshida

IPC分类号： H01L29/06

CPC分类号： H01L29/78609 ,  H01L21/26506 ,  H01L21/3221 ,  H01L21/3223 ,  H01L21/3226 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/32 ,  H01L29/7849 ,  H01L29/78603

摘要： In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.

摘要翻译： 在使用SOI衬底的SOI结构半导体器件中，通过将Ar离子注入作为有源层的硅衬底中形成晶格畸变层。 晶格畸变层能够用作吸杂位点。 调整Ar离子的剂量，使晶格变形层的拉伸应力为11MPa以上且27MPa以下。 因此，晶格畸变层可以防止在作为吸杂位置时发生漏电流。

公开(公告)号：US07985660B2

公开(公告)日：2011-07-26

申请号：US12450960

申请日：2008-04-16

申请人： Isao Yokokawa ,  Hiroshi Takeno ,  Nobuhiko Noto

发明人： Isao Yokokawa ,  Hiroshi Takeno ,  Nobuhiko Noto

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76256

摘要： The present invention provides a method for manufacturing an SOI wafer, including: a step of preparing a base wafer consisting of a p+ silicon single crystal wafer and a bond wafer consisting of a silicon single crystal wafer containing a dopant at a lower concentration than that in the base wafer; a step of forming a silicon oxide film on an entire surface of the base wafer based on thermal oxidation; a step of bonding the bond wafer to the base wafer through the silicon oxide film; and a step of reducing a thickness of the bond wafer to form an SOI layer, wherein a step of forming a CVD insulator film on a surface on an opposite side of a bonding surface of the base wafer is provided before the thermal oxidation step for the base wafer. As a result, it is possible to provide the method for manufacturing an SOI wafer which can easily prevent the p-type dopant contained in the base wafer from outwardly diffusing from the surface on the opposite side of the bonding surface of the base wafer due to a high-temperature heat treatment, suppress this dopant from being mixed into the SOI layer, and reduce warpage.

摘要翻译： 本发明提供一种制造SOI晶片的方法，包括：准备由p +硅单晶晶片构成的基底晶片和由含有掺杂剂的硅单晶晶片组成的接合晶片的步骤，其浓度低于 基片; 基于热氧化在基底晶片的整个表面上形成氧化硅膜的步骤; 通过氧化硅膜将接合晶片接合到基底晶片的步骤; 以及减小接合晶片的厚度以形成SOI层的步骤，其中在所述基底晶片的接合表面的相反侧的表面上形成CVD绝缘膜的步骤在所述基底晶片的接合表面的热氧化步骤之前提供 基片。 结果，可以提供一种制造SOI晶片的方法，其可以容易地防止基底晶片中包含的p型掺杂物从基底晶片的接合表面的相对侧上的表面向外扩散，这是由于 进行高温热处理，可以抑制该掺杂剂混入SOI层，从而降低翘曲。

公开(公告)号：US20100264510A1

公开(公告)日：2010-10-21

申请号：US12734240

申请日：2008-10-20

申请人： Hiroshi Ohtsuki ,  Mitsutaka Katada ,  Nobuhiko Noto ,  Hiroshi Takeno ,  Kazuhiko Yoshida

发明人： Hiroshi Ohtsuki ,  Mitsutaka Katada ,  Nobuhiko Noto ,  Hiroshi Takeno ,  Kazuhiko Yoshida

IPC分类号： H01L29/06 ,  H01L21/306

CPC分类号： H01L29/78609 ,  H01L21/26506 ,  H01L21/3221 ,  H01L21/3223 ,  H01L21/3226 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/32 ,  H01L29/7849 ,  H01L29/78603

摘要： In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.

摘要翻译： 在使用SOI衬底的SOI结构半导体器件中，通过将Ar离子注入作为有源层的硅衬底中形成晶格畸变层。 晶格畸变层能够用作吸杂位点。 调整Ar离子的剂量，使晶格变形层的拉伸应力为11MPa以上且27MPa以下。 因此，晶格畸变层可以防止在作为吸杂位置时发生漏电流。

公开(公告)号：US5598452A

公开(公告)日：1997-01-28

申请号：US524453

申请日：1995-09-06

申请人： Hiroshi Takeno ,  Ryoji Hoshi ,  Satoshi Ushio ,  Takao Takenaka

发明人： Hiroshi Takeno ,  Ryoji Hoshi ,  Satoshi Ushio ,  Takao Takenaka

IPC分类号： G01N23/207 ,  H01L21/66

CPC分类号： G01N23/207

摘要： According to the invention, it is sought to provide a method of evaluating single crystal of silicon, which permits determination of the amount of precipitated oxygen of even a sample having been heat treated and with unknown initial interstitial oxygen concentration. X-rays radiated from X-ray source 7 is converted by slit 6 into a thin, parallel incident X-ray beam 3 to be incident on sample single crystal 1. After adjusting the angle .theta.1 of sample with respect to the incident X-ray beam such as to satisfy Bragg conditions, diffracted X-rays 4 produced by diffraction on the sample single crystal 1 are coupled from the back side thereof through X-ray receiving slit 8 to scintillator 5 for intensity measurement. The amount of precipitated oxygen is calculated from the measured diffracted X-ray intensity.

摘要翻译： 根据本发明，寻求提供一种评估硅单晶的方法，其允许确定即使经热处理的样品和未知的初始间隙氧浓度的沉淀氧的量。 从X射线源7辐射的X射线被狭缝6转换为薄的平行的入射X射线束3，以入射到样品单晶1上。在调整样品相对于入射X射线的角度θ1后， 例如为了满足布拉格条件，由样品单晶1衍射产生的衍射X射线4从背面通过X射线接收狭缝8耦合到用于强度测量的闪烁体5。 从测量的衍射X射线强度计算沉淀氧的量。

公开(公告)号：US20060075957A1

公开(公告)日：2006-04-13

申请号：US10530557

申请日：2003-09-29

申请人： Hiroshi Takeno ,  Masahiro Sakurada ,  Takeshi Kobayashi

发明人： Hiroshi Takeno ,  Masahiro Sakurada ,  Takeshi Kobayashi

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/14 ,  C30B28/12

CPC分类号： C30B33/02 ,  C30B29/06 ,  H01L21/3225

摘要： The present invention provides an annealed wafer which has a wafer surface layer serving as a device fabricating region and having an excellent oxide film dielectric breakdown characteristic, and a wafer bulk layer in which oxide precipitates are present at a high density at the stage before the wafer is loaded into the device fabrication processes to give an excellent IG capability, and a method for manufacturing the annealed wafer. The present invention is directed to an annealed wafer obtained by performing heat treatment on a silicon wafer manufactured from a silicon single crystal grown by the Czochralski method, wherein a good chip yield of an oxide film dielectric breakdown characteristic in a region having at least a depth of up to 5 μm from a wafer surface is 95% or more, and a density of oxide precipitates detectable in the wafer bulk and each having a size not smaller than a size showing a gettering capability is not less than 1×109/cm3.

摘要翻译： 本发明提供了一种退火晶片，其具有用作器件制造区域的晶片表面层并且具有优异的氧化膜介电击穿特性，以及晶片本体层，其中氧化物沉淀物以高密度存在于晶片前的阶段 被加载到器件制造工艺中以提供优异的IG能力，以及用于制造退火晶片的方法。 本发明涉及通过对由通过切克劳斯基法生长的硅单晶制造的硅晶片进行热处理而获得的退火晶片，其中在具有至少一深度的区域中的氧化膜介电击穿特性的良好的芯片产量 从晶片表面达到5μm的母体的密度为95％以上，并且在晶片体中可检测到的氧化物析出物的密度和每个具有不小于显示吸气能力的尺寸的尺寸不小于1×10 9 / SUP> / cm 3。

公开(公告)号：US06858094B2

公开(公告)日：2005-02-22

申请号：US10380975

申请日：2001-09-14

申请人： Wei Feig Qu ,  Yoshinori Hayamizu ,  Hiroshi Takeno

发明人： Wei Feig Qu ,  Yoshinori Hayamizu ,  Hiroshi Takeno

IPC分类号： H01L21/208 ,  C30B33/00 ,  H01L21/322 ,  H01L21/324 ,  H01L29/06

CPC分类号： C30B29/06 ,  C30B33/00 ,  H01L21/3225

摘要： The present invention provides a silicon wafer having a DZ layer near a surface and an oxide precipitate layer in a bulk portion, wherein interstitial oxygen concentrations of the DZ layer, the oxide precipitate layer and a transition region between the DZ layer and the oxide precipitate layer are all 8 ppma or less, and an epitaxial silicon wafer, wherein an epitaxial layer is formed on a surface of the silicon wafer, as well as a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having an initial interstitial oxygen concentration of 10 to 25 ppma by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a first heat treatment at 950 to 1050° C. for 2 to 5 hours, a second heat treatment at 450 to 550° C. for 4 to 10 hours, a third heat treatment at 750 to 850° C. for 2 to 8 hours, and a fourth heat treatment at 950 to 1100° C. for 8 to 24 hours. Thus, there is provided a method for producing a silicon wafer of which high resistivity can surely be maintained even when the wafer is subjected to a heat treatment for device production.

摘要翻译： 本发明提供了一种在大部分表面附近具有DZ层和在本体部分中的氧化物沉淀层的硅晶片，其中DZ层的间隙氧浓度，氧化物沉淀层以及DZ层和氧化物沉淀层之间的过渡区域 全部为8ppma以下，外延硅晶片，其中在硅晶片的表面上形成外延层，以及制造硅晶片的方法，其包括生长具有初始间隙的硅单晶锭 氧浓度为10〜25ppma，将硅单晶锭加工成晶片，对晶片进行950〜1050℃的第一次热处理2〜5小时，在450℃进行第二次热处理 在550℃下进行4〜10小时，在750〜850℃下进行2〜8小时的第3次热处理，在950〜1100℃进行第4次热处理8〜24小时。 因此，提供了一种制造硅晶片的方法，其中即使当晶片经受用于器件生产的热处理时，也可以确保高电阻率。