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    Insulated gate semiconductor device
    1.
    发明授权
    Insulated gate semiconductor device 有权
    绝缘栅半导体器件

    公开(公告)号：US07528441B2

    公开(公告)日：2009-05-05

    申请号：US11839293

    申请日：2007-08-15

    Applicant: Hiroyasu Ishida ,  Tadashi Natsume

    Inventor： Hiroyasu Ishida ,  Tadashi Natsume

    IPC: H01L27/108

    CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/7811

    Abstract: Provided is an insulated gate semiconductor device. In the device, source regions are provided in the entire operation area and a first back gate region is provided below the source region between trenches. Moreover, a second back gate region connected to the first back gate region is provided outside of the source regions. Thereafter, a first electrode layer coming into contact with the source regions is provided in the entire operation area, and a second electrode layer coming into contact with the second back gate regions is provided around the first electrode layer. Accordingly, potentials can be individually applied to the first electrode layer and the second electrode layer. Thus, it is possible to perform control for preventing reverse flow caused by a parasitic diode.

    Abstract translation: 提供绝缘栅半导体器件。 在器件中，源区域设置在整个操作区域中，并且在沟槽之间的源极区域的下方提供第一后栅极区域。 此外，连接到第一背栅极区域的第二背栅极区域设置在源极区域的外部。 此后，在整个操作区域中设置与源极区域接触的第一电极层，并且在第一电极层周围设置与第二背栅极区域接触的第二电极层。 因此，电位可以单独施加到第一电极层和第二电极层。 因此，可以执行用于防止由寄生二极管引起的反向流动的控制。

    Method of processing semiconductor wafer
    2.
    发明授权
    Method of processing semiconductor wafer 有权
    半导体晶片的处理方法

    公开(公告)号：US07902053B2

    公开(公告)日：2011-03-08

    申请号：US12199547

    申请日：2008-08-27

    Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama

    Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama

    IPC: H01L21/20

    CPC classification number: H01L29/0634 ,  H01L21/26586

    Abstract: Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.

    Abstract translation: n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻在半导体衬底上交替进行至少三次以形成外延层的所有半导体层。 因此，半导体层的杂质浓度分布可以是均匀的，并且pn结可以垂直于晶片表面形成。 此外，半导体层各自可以形成为窄的宽度，使得其杂质浓度增加。 利用这种结构，可以实现高击穿电压和低电阻。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07777316B2

    公开(公告)日：2010-08-17

    申请号：US12239368

    申请日：2008-09-26

    Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama ,  Tetsuya Okada

    Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama ,  Tetsuya Okada

    IPC: H01L23/02 ,  H01L23/34

    CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.

    Abstract translation: 提供一种半导体器件，其中在具有超结结构的半导体区域的端部中设置围绕元件区域的绝缘区域。 由于元件区域中的耗尽层在绝缘区域中结束，元件区域的端部不形成为曲面形状。 换句话说，耗尽层没有内部电场集中的曲面。 因此，通过证明终端区域，不需要采取措施使耗尽层在水平方向上扩展。 由于不需要端子区域，因此可以减小芯片尺寸。 或者，可以扩展元件区域的区域。

    Semiconductor device and manufacturing method thereof
    6.
    发明申请
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US20050073004A1

    公开(公告)日：2005-04-07

    申请号：US10929727

    申请日：2004-08-31

    Applicant: Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

    Inventor： Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

    IPC: H01L29/06 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78 ,  H01L29/861

    CPC classification number: H01L29/7811 ,  H01L29/407 ,  H01L29/7813 ,  Y10S257/908

    Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

    Abstract translation: 常规的功率MOSFET能够防止围绕元件区域的外围的周围区域由宽的环形层和宽的密封金属引起的反转。 因此，由于周边地区的面积大，元素区域的增加受到限制。 因此提供了具有包含MIS（MOS）结构的反转防止区域的半导体器件。 用于防反转区域的多晶硅的宽度足够大以防止由于沟槽的深度增加氧化膜的面积而导致的反转。 由此，即使围绕元件区域的外周的区域的面积没有扩大，也可以减小泄漏电流。 此外，由于元件区域被扩大，MOSFET的导通电阻可以降低。

    Insulated-gate semiconductor device and PN junction diodes
    7.
    发明授权
    Insulated-gate semiconductor device and PN junction diodes 有权
    绝缘栅半导体器件和PN结二极管

    公开(公告)号：US07825474B2

    公开(公告)日：2010-11-02

    申请号：US11860206

    申请日：2007-09-24

    Applicant: Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    Inventor： Yasunari Noguchi ,  Eio Onodera ,  Hiroyasu Ishida

    IPC: H01L23/62 ,  H01L29/66

    CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/7804 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.

    Abstract translation: 与晶体管单元连续的沟道区也设置在栅极焊盘电极下方。 栅极焊盘电极下方的沟道区域固定为源极电位。 因此，确保漏极和源极之间的预定的反向击穿电压，而不在栅极焊盘电极的整个下表面下方形成p +型杂质区域。 此外，在设置在操作区域的外周的导电层中形成保护二极管。

    INSULATED GATE SEMICONDUCTOR DEVICE
    8.
    发明申请
    INSULATED GATE SEMICONDUCTOR DEVICE 有权
    绝缘栅半导体器件

    公开(公告)号：US20100163922A1

    公开(公告)日：2010-07-01

    申请号：US12645942

    申请日：2009-12-23

    Applicant: Shuji Yoneda ,  Hiroyasu Ishida ,  Makoto Oikawa

    Inventor： Shuji Yoneda ,  Hiroyasu Ishida ,  Makoto Oikawa

    IPC: H01L27/06

    CPC classification number: H01L27/0652 ,  H01L29/0696 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/866 ,  H03K17/163

    Abstract: By integrating a diode and a resistor connected in parallel into the same chip as an IGBT and connecting a cathode of the diode to a gate of the IGBT, the value of dv/dt can be limited to a predetermined range inside the chip of the IGBT without a deterioration in turn-on characteristics. Since the chip includes a resistor having such a resistance that a dv/dt breakdown of the IGBT can be prevented, the IGBT can be prevented from being broken by an increase in dv/dt at a site (user site) to which the chip is supplied.

    Abstract translation: 通过将二极管和电阻并联连接到与IGBT相同的芯片上并将二极管的阴极连接到IGBT的栅极，dv / dt的值可以限制在IGBT的芯片内部的预定范围内 没有导通特性的恶化。 由于芯片包括具有能够防止IGBT的dv / dt击穿的电阻的电阻器，因此可以防止IGBT在芯片的场所（用户现场）处的dv / dt增加而被破坏 提供。

    Insulated gate semiconductor device
    9.
    发明授权
    Insulated gate semiconductor device 有权
    绝缘栅半导体器件

    公开(公告)号：US07692240B2

    公开(公告)日：2010-04-06

    申请号：US11797900

    申请日：2007-05-08

    Applicant: Hiroyasu Ishida ,  Yasunari Noguchi

    Inventor： Hiroyasu Ishida ,  Yasunari Noguchi

    IPC: H01L29/94

    CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

    Abstract: Channel regions and gate electrodes are also disposed continuously with transistor cells below a gate pad electrode. The transistor cells are formed in a stripe pattern and allowed to contact a source electrode. In this way, the channel regions and the gate electrodes, which are positioned below the gate pad electrode, are kept at a predetermined potential. Thus, a predetermined drain-source reverse breakdown voltage can be secured without providing a p+ type impurity region on the entire surface below the gate pad electrode.

    Abstract translation: 通道区域和栅电极也与栅极焊盘电极下面的晶体管单元连续地设置。 晶体管单元形成为条状图案并允许与源极接触。 以这种方式，位于栅极焊盘电极下方的沟道区域和栅极电极保持在预定电位。 因此，可以确保在栅极电极下方的整个表面上不设置p +型杂质区域的预定的漏极 - 反向击穿电压。

    Semiconductor device with peripheral trench
    10.
    发明授权
    Semiconductor device with peripheral trench 有权
    具有外围沟槽的半导体器件

    公开(公告)号：US07230300B2

    公开(公告)日：2007-06-12

    申请号：US10929727

    申请日：2004-08-31

    Applicant: Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

    Inventor： Masahito Onda ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Hiroyasu Ishida

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/7811 ,  H01L29/407 ,  H01L29/7813 ,  Y10S257/908

    Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

    Abstract translation: 常规的功率MOSFET能够防止围绕元件区域的外围的周围区域由宽的环形层和宽的密封金属引起的反转。 因此，由于周边地区的面积大，元素区域的增加受到限制。 因此提供了具有包含MIS（MOS）结构的反转防止区域的半导体器件。 用于防反转区域的多晶硅的宽度足够大以防止由于沟槽的深度增加氧化膜的面积而导致的反转。 由此，即使围绕元件区域的外周的区域的面积没有扩大，也可以减小泄漏电流。 此外，由于元件区域被扩大，MOSFET的导通电阻可以降低。

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