公开(公告)号：US06849885B2

公开(公告)日：2005-02-01

申请号：US10626768

申请日：2003-07-25

申请人： Hiroyuki Enomoto ,  Hiroyuki Maruyama ,  Makoto Yoshida

发明人： Hiroyuki Enomoto ,  Hiroyuki Maruyama ,  Makoto Yoshida

IPC分类号： H01L21/302 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L21/76831 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

摘要： An amount of a semiconductor substrate cut due to etching in the bottom of a contact hole formed by the SAC technique is reduced. Silicon oxide films are dry etched under the conditions of increasing the etching selective ratio of the silicon oxide films to an insulating film. Then, the conditions are changed to those increasing the etching selective ratio of the insulating film to the silicon oxide films and the insulating film is etched by a predetermined amount.

摘要翻译： 通过在SAC技术形成的接触孔的底部的蚀刻而切割的半导体衬底的量减少。 在增加氧化硅膜与绝缘膜的蚀刻选择比的条件下，对氧化硅膜进行干蚀刻。 然后，将条件改变为提高绝缘膜与氧化硅膜的蚀刻选择比的那些，并且绝缘膜被蚀刻预定量。

公开(公告)号：US06482727B2

公开(公告)日：2002-11-19

申请号：US10036449

申请日：2002-01-07

申请人： Hiroyuki Enomoto ,  Hiroyuki Maruyama ,  Makoto Yoshida

发明人： Hiroyuki Enomoto ,  Hiroyuki Maruyama ,  Makoto Yoshida

IPC分类号： H01L213205

CPC分类号： H01L21/76831 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

摘要： An amount of a semiconductor substrate cut due to etching in the bottom of a contact hole formed by the SAC technique is reduced. Silicon oxide films are dry etched under the conditions of increasing the etching selective ratio of the silicon oxide films to an insulating film. Then, the conditions are changed to those increasing the etching selective ratio of the insulating film to the silicon oxide films and the insulating film is etched by a predetermined amount.

公开(公告)号：US08012871B2

公开(公告)日：2011-09-06

申请号：US12771494

申请日：2010-04-30

申请人： Kazutoshi Ohmori ,  Tsuyoshi Tamaru ,  Naohumi Ohashi ,  Kiyohiko Sato ,  Hiroyuki Maruyama

发明人： Kazutoshi Ohmori ,  Tsuyoshi Tamaru ,  Naohumi Ohashi ,  Kiyohiko Sato ,  Hiroyuki Maruyama

IPC分类号： H01L21/4763

CPC分类号： H01L21/76829 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76832 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.

摘要翻译： 提供一种半导体器件及其制造方法，用于提高布线层之间的膜和通孔层之间的膜由具有低介电常数的SiOC膜构成的铜镶嵌线的可靠性的提高。 布线层之间的膜，布线层之间的膜和通孔层之间的膜分别由SiOC膜构成，并且阻挡绝缘膜和帽绝缘膜由SiCN膜A和SiC膜的层压膜构成 通过这样做，可以减少布线层之间的膜，布线层之间的膜和通孔层之间的膜的漏电流，并且还可以提高布线层之间的膜的粘附性，膜 布线层之间的通孔层与阻挡绝缘膜和帽绝缘膜之间的膜。

公开(公告)号：US20100210107A1

公开(公告)日：2010-08-19

申请号：US12771494

申请日：2010-04-30

申请人： Kazutoshi Ohmori ,  Tsuyoshi Tamaru ,  Naohumi Ohashi ,  Kiyohiko Sato ,  Hiroyuki Maruyama

发明人： Kazutoshi Ohmori ,  Tsuyoshi Tamaru ,  Naohumi Ohashi ,  Kiyohiko Sato ,  Hiroyuki Maruyama

IPC分类号： H01L21/768

CPC分类号： H01L21/76829 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76832 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.

摘要翻译： 提供一种半导体器件及其制造方法，用于提高布线层之间的膜和通孔层之间的膜由具有低介电常数的SiOC膜构成的铜镶嵌线的可靠性的提高。 布线层之间的膜，布线层之间的膜和通孔层之间的膜分别由SiOC膜构成，并且阻挡绝缘膜和帽绝缘膜由SiCN膜A和SiC膜的层压膜构成 通过这样做，可以减少布线层之间的膜，布线层之间的膜和通孔层之间的膜的漏电流，并且还可以提高布线层之间的膜的粘附性，膜 布线层之间的通孔层与阻挡绝缘膜和帽绝缘膜之间的膜。

公开(公告)号：US07542058B2

公开(公告)日：2009-06-02

申请号：US11126129

申请日：2005-05-10

申请人： Eiji Nishikawa ,  Hiroyuki Maruyama ,  Hiroyuki Arai ,  Toshihiro Motoi ,  Kenji Izumiya ,  Ryuji Okutomi ,  Shinobu Kishi ,  Satoshi Ogata ,  Kenichi Ozawa ,  Tadayuki Ueda ,  Yumiko Higashi

发明人： Eiji Nishikawa ,  Hiroyuki Maruyama ,  Hiroyuki Arai ,  Toshihiro Motoi ,  Kenji Izumiya ,  Ryuji Okutomi ,  Shinobu Kishi ,  Satoshi Ogata ,  Kenichi Ozawa ,  Tadayuki Ueda ,  Yumiko Higashi

IPC分类号： G03G15/01

CPC分类号： B41J29/393 ,  G03G15/0194 ,  G03G2215/0119 ,  G03G2215/0161 ,  G06K15/129 ,  H04N1/506

摘要： In an image forming apparatus for forming a color image by superposing component color images, a control device obtains position data representing a forming position of each of plural registration mark images for the component color images with respect to a positional reference value arbitrarily determined, divides the position data into each of a unit reference range representing a range in which one mark image is formed, converts the position data divided for each unit reference range into those based on respective reference values representing the front edge of the unit reference ranges, extracts the position data representing ranges common to the mutually overlapping ranges each of which is representing by a couple of position data corresponding to the rising and falling edges of a passage timing pulse as read position data of the mark image of the component color, and calculates the amounts of positional deviations of the component color images from one another on the basis of the position data extracted.

摘要翻译： 在通过叠加分量彩色图像形成彩色图像的图像形成装置中，控制装置获取表示相对于任意确定的位置基准值的分量彩色图像的多个对准标记图像中的每一个的形成位置的位置数据， 将位置数据分配到表示形成一个标记图像的范围的单位基准范围的每一个中，根据表示单位基准范围的前沿的各个基准值，将每个单位基准范围划分的位置数据转换为基准值， 数据表示相互重叠的范围共同的范围，每个范围通过对应于通过定时脉冲的上升沿和下降沿的一对位置数据表示为分量颜色的标记图像的读取位置数据，并且计算 基于此，分量彩色图像彼此的位置偏差 提取位置数据。

公开(公告)号：US07460213B2

公开(公告)日：2008-12-02

申请号：US11925026

申请日：2007-10-26

申请人： Hiroyuki Maruyama

发明人： Hiroyuki Maruyama

IPC分类号： G03B27/58

CPC分类号： G03F7/70933 ,  G03F7/70758 ,  G03F7/70775 ,  G03F7/70858

摘要： An alignment apparatus includes driving means having a movable element and a stator, a measurement unit which measures a position of a moving member moved by the driving means using measurement light, and a discharging unit to discharge gas existing in an optical path of the measurement light. The discharging unit is provided to the stator.

摘要翻译： 对准装置包括具有可移动元件和定子的驱动装置，测量单元，其测量由驱动装置利用测量光移动的移动构件的位置;以及放电单元，用于排出存在于测量光的光路中的气体 。 放电单元设置在定子上。

公开(公告)号：US20080056790A1

公开(公告)日：2008-03-06

申请号：US11882923

申请日：2007-08-07

申请人： Hiroyuki Maruyama

发明人： Hiroyuki Maruyama

IPC分类号： G03G15/00

CPC分类号： G03G15/6567 ,  G03G15/235 ,  G03G15/6564

摘要： A sheet conveying apparatus which conveys a recording sheet fed from a sheet feeding section toward a transfer position with controlled timing, including: a pair of registration rollers; a pair of loop rollers to form a loop of the recording sheet, the loop rollers being disposed upstream of the registration rollers in a sheet feeding direction; and a movable conveying unit configured such that the registration rollers and the loop rollers move as a unified body when correcting at least a lateral misalignment, which is a misalignment in a vertical direction to the sheet feeding direction, and inclination of the recording sheet.

摘要翻译： 一种纸张输送装置，其将从纸张供给部供给到具有受控定时的转印位置的记录纸输送，包括：一对定位辊; 一对环形辊，以形成记录纸的环，所述环形辊在纸张进给方向上设置在所述对位辊的上游; 以及可移动输送单元，其构造成使得当校正至少一个垂直方向与片材进给方向不对准的横向偏移和记录片材的倾斜时，定位辊和环形辊作为统一的主体移动。

公开(公告)号：US07208391B2

公开(公告)日：2007-04-24

申请号：US11149538

申请日：2005-06-10

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

公开(公告)号：US07201016B2

公开(公告)日：2007-04-10

申请号：US10776168

申请日：2004-02-12

申请人： Hiroyuki Maruyama

发明人： Hiroyuki Maruyama

IPC分类号： F25B43/04

CPC分类号： H01L21/67109 ,  G03F7/70758 ,  G03F7/70858

摘要： A refrigerant supply apparatus for supplying a refrigerant to a cooling target. The apparatus includes a refrigerant supply channel through which pure water as the refrigerant is supplied to the cooling target, an impurity removing unit disposed in an impurity removing channel which is a channel different from the refrigerant supply channel, a sensor which measures a purity of the pure water, and a valve which stops supply of the pure water to the cooling target when the purity of the pure water does not satisfy a predetermined standard.

摘要翻译： 一种用于向冷却对象供给制冷剂的制冷剂供给装置。 该装置包括制冷剂供给通道，通过该制冷剂供给通道将作为制冷剂的纯水供给到冷却对象，杂质除去单元，设置在不同于制冷剂供给通道的通道的杂质去除通道中，测量纯度的传感器 纯水以及当纯水的纯度不满足预定标准时停止向冷却对象供应纯水的阀。

公开(公告)号：US20050239257A1

公开(公告)日：2005-10-27

申请号：US11149538

申请日：2005-06-10

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/76 ,  G02B17/00 ,  G02B21/00 ,  G02B23/00 ,  H01L21/302 ,  H01L21/312 ,  H01L21/316 ,  H01L21/461 ,  H01L21/762 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.