公开(公告)号：US20100090338A1

公开(公告)日：2010-04-15

申请号：US12393109

申请日：2009-02-26

申请人： Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

发明人： Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

IPC分类号： H01L23/522 ,  H01L25/11 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01055 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

摘要： A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.

摘要翻译： 微电子结构包括在衬底上的导电焊盘。 导电垫包括延伸穿过其中的第一和第二开口。 导电焊盘上的第一导电通孔延伸穿过导电焊盘中的第一开口进入衬底。 邻近第一导电通孔的导电焊盘上的第二导电通孔延伸穿过导电焊盘中的第二开口进入衬底。 导电通孔中的至少一个可以与导电焊盘电绝缘。 还讨论了相关设备和制造方法。

公开(公告)号：US08362621B2

公开(公告)日：2013-01-29

申请号：US12393109

申请日：2009-02-26

申请人： Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

发明人： Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

IPC分类号： H01L23/522 ,  H01L25/11

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01055 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

摘要： A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.

摘要翻译： 微电子结构包括在衬底上的导电焊盘。 导电垫包括延伸穿过其中的第一和第二开口。 导电焊盘上的第一导电通孔延伸穿过导电焊盘中的第一开口进入衬底。 邻近第一导电通孔的导电焊盘上的第二导电通孔延伸穿过导电焊盘中的第二开口进入衬底。 导电通孔中的至少一个可以与导电焊盘电绝缘。 还讨论了相关设备和制造方法。

公开(公告)号：US06903451B1

公开(公告)日：2005-06-07

申请号：US09723953

申请日：2000-11-27

申请人： Nam Seog Kim ,  Dong Hyeon Jang ,  Sa Yoon Kang ,  Heung Kyu Kwon

发明人： Nam Seog Kim ,  Dong Hyeon Jang ,  Sa Yoon Kang ,  Heung Kyu Kwon

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L29/06 ,  H01L23/02

CPC分类号： H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer are provided. The reinforcing layer absorbs stress applied to the bumps when the CSP is mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

摘要翻译： 根据本发明，在晶片级制造芯片级封装（CSP）。 CSP包括芯片，用于芯片的芯片焊盘重新分配的导体层，一个或两个绝缘层和多个凸起，其通过导体层互连到相应的芯片焊盘，并且是CSP的端子。 此外，为了提高CSP的可靠性，提供了增强层，边缘保护层和芯片保护层。 当CSP安装在电路板上并且长时间使用时，加强层吸收施加到凸起的应力，并延长凸块的寿命，从而延长CSP的寿命。 边缘保护层和芯片保护层防止外力损坏CSP。 在半导体晶片上形成构成CSP的所有元件之后，锯切半导体晶片以产生单独的CSP。

公开(公告)号：US06555921B2

公开(公告)日：2003-04-29

申请号：US09982338

申请日：2001-10-17

申请人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Nam Seog Kim ,  Dong Hyeon Jang

发明人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Nam Seog Kim ,  Dong Hyeon Jang

IPC分类号： H01L2348

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/12 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The semiconductor package further includes external terminals, interconnection bumps on the chip pads, and polymer protection layers on the solder fillings.

公开(公告)号：US06187615B1

公开(公告)日：2001-02-13

申请号：US09222250

申请日：1998-12-28

申请人： Nam Seog Kim ,  Dong Hyeon Jang ,  Sa Yoon Kang ,  Heung Kyu Kwon

发明人： Nam Seog Kim ,  Dong Hyeon Jang ,  Sa Yoon Kang ,  Heung Kyu Kwon

IPC分类号： H01L2144

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/11 ,  H01L24/12 ,  H01L29/0657 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/013

摘要： In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer is provided. The reinforcing layer absorbs stress applied to the bumps when the CSP are mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

摘要翻译： 根据本发明，在晶片级制造芯片级封装（CSP）。 CSP包括芯片，用于芯片的芯片焊盘重新分配的导体层，一个或两个绝缘层和多个凸块，其通过导体层互连到相应的芯片焊盘，并且是CSP的端子。 此外，为了提高CSP的可靠性，提供了增强层，边缘保护层和芯片保护层。 当CSP安装在电路板上并且长时间使用时，加强层吸收施加到凸起的应力，延长凸块的寿命，从而延长CSP的寿命。 边缘保护层和芯片保护层防止外力损坏CSP。 在半导体晶片上形成构成CSP的所有元件之后，锯切半导体晶片以产生单独的CSP。

公开(公告)号：US06376279B1

公开(公告)日：2002-04-23

申请号：US09482216

申请日：2000-01-12

申请人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Nam Seog Kim ,  Dong Hyeon Jang

发明人： Yong Hwan Kwon ,  Sa Yoon Kang ,  Nam Seog Kim ,  Dong Hyeon Jang

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/12 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film. The semiconductor package includes: an integrated circuit having chip pads; a substrate attached to the integrated circuit so that via holes of the substrate are above the chip pads; solder fillings inside the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The semiconductor package further includes external terminals, interconnection bumps on the chip pads, and polymer protection layers on the solder fillings.

摘要翻译： 半导体封装制造方法包括：提供重新布线膜; 将具有集成电路的半导体晶片连接到重新布线膜，使得集成电路的芯片焊盘对应于重新布线膜的通孔; 在每个所述通孔中形成焊料填充物，以将所述芯片焊盘电连接到所述金属图案层; 在重新布线膜的端子焊盘上形成外部端子; 以及将所述晶片和所述重新布线膜分离成单独的半导体封装。 一种方法还包括在焊料填充物上形成保护层。 代替半导体晶片，各个集成电路芯片可以附着在重新布线的薄膜上。 半导体封装包括：具有芯片焊盘的集成电路; 附着到集成电路的衬底，使得衬底的通孔位于芯片焊盘之上; 通孔内的焊料填充物，焊料填充物将芯片焊盘电连接到图案金属层; 以及衬底和半导体集成电路之间的另一介质层。 半导体封装还包括外部端子，芯片焊盘上的互连凸块和焊料填充物上的聚合物保护层。

公开(公告)号：US06340838B1

公开(公告)日：2002-01-22

申请号：US09241655

申请日：1999-02-02

申请人： Tae Gyeong Chung ,  Nam Seog Kim

发明人： Tae Gyeong Chung ,  Nam Seog Kim

IPC分类号： G01R3102

CPC分类号： H01R4/5066 ,  G01R1/0483 ,  H01L2224/73253 ,  H01R13/22

摘要： An apparatus for identifying a known good die according to an embodiment of the present invention includes a carrier for containing a bare semiconductor chip, a lid for covering the carrier, and a stopper for sealing the apparatus. The carrier includes: a body, in which a chip mount cavity and multiple vacuum suction holes are formed; inner connection terminals formed on a bottom surface of the chip mount cavity to communicate electrically with the bare chip; and outer connection terminals extending from the inner connection terminals to outside the body. The apparatus has an outer configuration of a conventional semiconductor package, so that the apparatus can fit into conventional test equipment. Therefore, the carrier can have a configuration of a plastic package, such as the SOP or SOJ, without a semiconductor chip. Accordingly, the apparatus according to the present invention can use conventional handling and burn-in test equipment in identifying of known good dies and thereby reduce production cost of the known good dies.

摘要翻译： 根据本发明的实施例的用于识别已知的良好裸片的装置包括用于容纳裸半导体芯片的载体，用于覆盖载体的盖和用于密封该装置的止动件。 载体包括：其中形成有芯片安装腔和多个真空吸孔的主体; 内部连接端子形成在芯片安装腔的底表面上以与裸芯片电气连通; 以及从内部连接端子延伸到主体外部的外部连接端子。 该装置具有常规半导体封装的外部结构，使得该装置可以装配到常规的测试设备中。 因此，载体可以具有没有半导体芯片的诸如SOP或SOJ的塑料封装的构造。 因此，根据本发明的装置可以使用常规的处理和老化测试设备来识别已知的良好模具，从而降低已知的良好模具的生产成本。