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公开(公告)号：US20100032830A1
公开(公告)日：2010-02-11
申请号：US12500780
申请日：2009-07-10
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L21/76898 , H01L24/20 , H01L24/24 , H01L24/82 , H01L27/14618 , H01L27/14643 , H01L27/14683 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/05569 , H01L2224/0557 , H01L2224/05571 , H01L2224/12105 , H01L2224/24226 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/1461 , H01L2924/15311 , H01L2924/15788 , H01L2924/00
摘要： The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion, both of which constitute a recess communicating with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.
摘要翻译： 三维导电结构包括衬底，第一再分布导体，第二再分布导体和绝缘体。 衬底具有活性表面，与活性表面相对的无源表面，活性表面上的焊盘和通孔。 第一再分布导体包括突出部分和接收部分。 突出部分从有源表面突出并电连接到焊盘。 接收部分在活性表面之外并且与突出部分接触，两者都构成与通孔连通的凹部。 第二再分布导体定位在通孔内，凹部与接收部分接触，并沿着通孔向被动表面延伸。 绝缘体填充在第二再分布导体和衬底之间以及第二再分布导体和突出部分之间。
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公开(公告)号：US08193632B2
公开(公告)日：2012-06-05
申请号：US12500780
申请日：2009-07-10
IPC分类号： H01L23/04
CPC分类号： H01L21/76898 , H01L24/20 , H01L24/24 , H01L24/82 , H01L27/14618 , H01L27/14643 , H01L27/14683 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/05569 , H01L2224/0557 , H01L2224/05571 , H01L2224/12105 , H01L2224/24226 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/1461 , H01L2924/15311 , H01L2924/15788 , H01L2924/00
摘要： The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion, both of which constitute a recess communicating with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.
摘要翻译： 三维导电结构包括衬底，第一再分布导体，第二再分布导体和绝缘体。 衬底具有活性表面，与活性表面相对的无源表面，活性表面上的焊盘和通孔。 第一再分布导体包括突出部分和接收部分。 突出部分从有源表面突出并电连接到焊盘。 接收部分在活性表面之外并且与突出部分接触，两者都构成与通孔连通的凹部。 第二再分布导体定位在通孔内，凹部与接收部分接触，并沿着通孔向被动表面延伸。 绝缘体填充在第二再分布导体和衬底之间以及第二再分布导体和突出部分之间。
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公开(公告)号：US07663231B2
公开(公告)日：2010-02-16
申请号：US12010617
申请日：2008-01-28
IPC分类号： H01L23/34
CPC分类号： H01L27/14618 , H01L24/19 , H01L24/24 , H01L24/97 , H01L25/0657 , H01L25/16 , H01L27/14634 , H01L2223/6677 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/051 , H01L2224/0557 , H01L2224/05571 , H01L2224/12105 , H01L2224/24145 , H01L2224/32145 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/00014 , H01L2924/12041 , H01L2924/15311 , H01L2924/19103 , H01L2924/19104 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2224/05599
摘要： This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.
摘要翻译： 本发明提供一种具有三维管芯堆叠结构的图像传感器模块。 通过将导电材料填充到至少一个图像传感器芯片内的通孔硅中，并且在绝缘层内的通孔中，在图像传感器裸片和埋在绝缘层中的图像处理器之间形成垂直电连接。 多个焊料凸块形成在图像传感器模块的背面，使得模块可以直接组装到电路板上。 本发明的图像传感器模块的特征在于晶片级封装结构和三维管芯堆叠结构，其减小了模块内的电连接长度，从而减小了整个封装模块的面积和高度。
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公开(公告)号：US20080308928A1
公开(公告)日：2008-12-18
申请号：US12010617
申请日：2008-01-28
IPC分类号： H01L23/34
CPC分类号： H01L27/14618 , H01L24/19 , H01L24/24 , H01L24/97 , H01L25/0657 , H01L25/16 , H01L27/14634 , H01L2223/6677 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/051 , H01L2224/0557 , H01L2224/05571 , H01L2224/12105 , H01L2224/24145 , H01L2224/32145 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/00014 , H01L2924/12041 , H01L2924/15311 , H01L2924/19103 , H01L2924/19104 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2224/05599
摘要： This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.
摘要翻译： 本发明提供一种具有三维管芯堆叠结构的图像传感器模块。 通过将导电材料填充到至少一个图像传感器芯片内的通孔硅中，并且在绝缘层内的通孔中，在图像传感器裸片和埋在绝缘层中的图像处理器之间形成垂直电连接。 多个焊料凸块形成在图像传感器模块的背面，使得模块可以直接组装到电路板上。 本发明的图像传感器模块的特征在于晶片级封装结构和三维管芯堆叠结构，其减小了模块内的电连接长度，从而减小了整个封装模块的面积和高度。
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公开(公告)号：US20120133046A1
公开(公告)日：2012-05-31
申请号：US13037372
申请日：2011-03-01
申请人： Chun-Hsien Chien , John H. Lau , Hsiang-Hung Chang , Huan-Chun Fu , Tzu-Ying Kuo , Wen-Li Tsai
发明人： Chun-Hsien Chien , John H. Lau , Hsiang-Hung Chang , Huan-Chun Fu , Tzu-Ying Kuo , Wen-Li Tsai
CPC分类号： H01L23/481 , H01L21/6835 , H01L23/562 , H01L23/585 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2221/68327 , H01L2221/68372 , H01L2224/02372 , H01L2224/03002 , H01L2224/0401 , H01L2224/05009 , H01L2224/05569 , H01L2224/0603 , H01L2224/06182 , H01L2224/11002 , H01L2224/13025 , H01L2224/93 , H01L2224/94 , H01L2924/00014 , H01L2924/01023 , H01L2924/01033 , H01L2224/0231 , H01L2224/03 , H01L2224/11 , H01L2224/05552
摘要： A semiconductor structure and a process thereof are provided. The semiconductor structure includes a semiconductor wafer having a first surface and a second surface opposite to the first surface, through silicon vias and a crack stopping slot. The through silicon vias are embedded in the semiconductor wafer and connected between the first surface and the second surface. The crack stopping slot is located in the periphery of the second surface of the semiconductor wafer. The depth of the crack stopping slot is less than or equal to the thickness of the semiconductor wafer. The process firstly provides a semiconductor wafer having through silicon vias. Then, the aforementioned crack stopping slot is formed at a back side of the semiconductor wafer opposite to the first surface. Next, the semiconductor wafer is thinned from the back side to expose a second end of each through silicon via.
摘要翻译： 提供半导体结构及其工艺。 半导体结构包括具有第一表面和与第一表面相对的第二表面的半导体晶片，通过硅通孔和裂纹停止槽。 贯通硅通孔嵌入在半导体晶片中并连接在第一表面和第二表面之间。 裂纹停止槽位于半导体晶片的第二表面的周边。 裂纹停止槽的深度小于或等于半导体晶片的厚度。 该方法首先提供具有硅通孔的半导体晶片。 然后，在半导体晶片的与第一表面相对的背面形成上述裂纹停止槽。 接下来，半导体晶片从背面变薄以暴露出每个通过硅通孔的第二端。
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公开(公告)号：US07902674B2
公开(公告)日：2011-03-08
申请号：US12155715
申请日：2008-06-09
申请人： Hsiang-Hung Chang , Shu-Ming Chang
发明人： Hsiang-Hung Chang , Shu-Ming Chang
IPC分类号： H01L21/31
CPC分类号： H01L21/76898 , H01L21/6835 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2221/68377 , H01L2224/02372 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/056 , H01L2224/13025 , H01L2224/16 , H01L2224/24145 , H01L2224/274 , H01L2224/29101 , H01L2224/2919 , H01L2224/32188 , H01L2224/9202 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/05099
摘要： This invention provides a substrate having at least one bottom electrode formed therein. A plurality of dice each having at least one opening formed therein are vertically stacked together one by one by a polymer insulating layer acting as an adhering layer between them, along with the openings thereof aligned to each other to form a through hole passing through said dice. The stacked dice are joined to a bottom of the substrate with the polymer insulating layer acting as an adhering layer, making the bottom electrode of the substrate contact the through hole. An electroplating process is performed with the bottom electrode serving as an electroplating electrode to form a conductive contact passing through the dice.
摘要翻译： 本发明提供一种其中形成有至少一个底部电极的基板。 每个具有形成在其中的至少一个开口的多个骰子通过在其间作为粘合层的聚合物绝缘层一个接一个地垂直堆叠在一起，并且其开口彼此对准以形成穿过所述骰子的通孔 。 堆叠的骰子连接到基底的底部，聚合物绝缘层用作粘合层，使得基底的底部电极与通孔接触。 执行电镀工艺，其中底部电极用作电镀电极，以形成通过芯片的导电接触。
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7.发明申请公开(公告)号：US20090014891A1
公开(公告)日：2009-01-15
申请号：US12155715
申请日：2008-06-09
申请人： Hsiang-Hung Chang , Shu-Ming Chang
发明人： Hsiang-Hung Chang , Shu-Ming Chang
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L21/76898 , H01L21/6835 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2221/68377 , H01L2224/02372 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/056 , H01L2224/13025 , H01L2224/16 , H01L2224/24145 , H01L2224/274 , H01L2224/29101 , H01L2224/2919 , H01L2224/32188 , H01L2224/9202 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/05099
摘要： This invention provides a substrate having at least one bottom electrode formed therein. A plurality of dice each having at least one opening formed therein are vertically stacked together one by one by a polymer insulating layer acting as an adhering layer between them, along with the openings thereof aligned to each other to form a through hole passing through said dice. The stacked dice are joined to a bottom of the substrate with the polymer insulating layer acting as an adhering layer, making the bottom electrode of the substrate contact the through hole. An electroplating process is performed with the bottom electrode serving as an electroplating electrode to form a conductive contact passing through the dice.
摘要翻译： 本发明提供一种其中形成有至少一个底部电极的基板。 每个具有形成在其中的至少一个开口的多个骰子通过在其间作为粘合层的聚合物绝缘层一个接一个地垂直堆叠在一起，并且其开口彼此对准以形成穿过所述骰子的通孔 。 堆叠的骰子连接到基底的底部，聚合物绝缘层用作粘合层，使得基底的底部电极与通孔接触。 执行电镀工艺，其中底部电极用作电镀电极，以形成通过芯片的导电接触。
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