公开(公告)号：US20080110669A1

公开(公告)日：2008-05-15

申请号：US11976760

申请日：2007-10-26

申请人： Hwa Sun Park ,  Tae Eui Kim ,  Jong Kuk Hong ,  Sang Jin Baek ,  Hong Won Kim ,  Jin Soo Jeong

发明人： Hwa Sun Park ,  Tae Eui Kim ,  Jong Kuk Hong ,  Sang Jin Baek ,  Hong Won Kim ,  Jin Soo Jeong

IPC分类号： H05K1/16 ,  H05K3/30

CPC分类号： H05K1/167 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09481 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： Disclosed herein is a Printed Circuit Board (PCB) having embedded resistors and a method of manufacturing the same, in which contact pads are formed by filling via holes formed on electrode pads with oxidation-resistant conductive material, and resistors are formed on the contact pads. Accordingly, erosion that occurs between the electrode pads and the resistors can be prevented using the contact pads made of oxidation-resistant conductive material, and connections between circuits also can be realized. Furthermore, resistors are formed on a flat plane without any difference in height, attributable to the electrode pads, and thus differences between the resistance values of the built-in resistors can be greatly reduced.

摘要翻译： 本文公开了具有嵌入式电阻器的印刷电路板（PCB）及其制造方法，其中通过在电极焊盘上形成的具有抗氧化导电材料的孔填充形成接触焊盘，并且在接触焊盘上形成电阻器 。 因此，可以使用由抗氧化导电材料制成的接触垫来防止在电极焊盘和电阻器之间发生的侵蚀，并且还可以实现电路之间的连接。 此外，电阻器形成在平面上，由于电极焊盘而在高度上没有任何差异，因此可以大大降低内置电阻器的电阻值之间的差异。

公开(公告)号：US20100269335A1

公开(公告)日：2010-10-28

申请号：US12801870

申请日：2010-06-29

申请人： Hwa Sun Park ,  Tae Eui Kim

发明人： Hwa Sun Park ,  Tae Eui Kim

IPC分类号： H05K3/10

CPC分类号： H05K1/167 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09481 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of manufacturing a printed circuit board (PCB) having embedded resistors, including providing a PCB on which internal layer circuit patterns, including electrode pads, are formed; layering insulating layers on the PCB; forming first via holes on the electrode pads and simultaneously forming second via holes at predetermined locations on the internal layer circuit patterns; forming contact pads for connecting the electrode pads with resistors by filling the first via holes with oxidation-resistant conductive material and flattening the oxidation-resistant conductive material; forming the resistors so that ends of each resistor are connected to two respective contact pads, which are spaced apart from each other; forming circuit patterns on the PCB, in which the second via holes are formed; and layering insulting layers on the PCB having the formed circuit patterns, and forming external layer circuit patterns.

摘要翻译： 一种具有嵌入式电阻器的印刷电路板（PCB）的制造方法，其特征在于，提供形成有包含电极焊盘的内层电路图案的PCB; 在PCB上分层绝缘层; 在电极焊盘上形成第一通孔并同时在内层电路图形上的预定位置形成第二通孔; 形成用于通过用耐氧化导电材料填充第一通孔并使抗氧化导电材料变平的方式将电极焊盘与电阻器连接的接触焊盘; 形成电阻器，使得每个电阻器的端部连接到彼此间隔开的两个相应的接触焊盘; 在PCB上形成电路图案，其中形成第二通孔; 以及在PCB上具有形成的电路图案的层叠绝缘层，以及形成外部层电路图案。

公开(公告)号：US08166653B2

公开(公告)日：2012-05-01

申请号：US12801870

申请日：2010-06-29

申请人： Hwa Sun Park ,  Tae Eui Kim

发明人： Hwa Sun Park ,  Tae Eui Kim

IPC分类号： H01K3/10

CPC分类号： H05K1/167 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09481 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of manufacturing a printed circuit board (PCB) having embedded resistors, including providing a PCB on which internal layer circuit patterns, including electrode pads, are formed; layering insulating layers on the PCB; forming first via holes on the electrode pads and simultaneously forming second via holes at predetermined locations on the internal layer circuit patterns; forming contact pads for connecting the electrode pads with resistors by filling the first via holes with oxidation-resistant conductive material and flattening the oxidation-resistant conductive material; forming the resistors so that ends of each resistor are connected to two respective contact pads, which are spaced apart from each other; forming circuit patterns on the PCB, in which the second via holes are formed; and layering insulting layers on the PCB having the formed circuit patterns, and forming external layer circuit patterns.

摘要翻译： 一种具有嵌入式电阻器的印刷电路板（PCB）的制造方法，其特征在于，提供形成有包含电极焊盘的内层电路图案的PCB; 在PCB上分层绝缘层; 在电极焊盘上形成第一通孔并同时在内层电路图形上的预定位置形成第二通孔; 形成用于通过用耐氧化导电材料填充第一通孔并使抗氧化导电材料变平的方式将电极焊盘与电阻器连接的接触焊盘; 形成电阻器，使得每个电阻器的端部连接到彼此间隔开的两个相应的接触焊盘; 在PCB上形成电路图案，其中形成第二通孔; 以及在PCB上具有形成的电路图案的层叠绝缘层，以及形成外部层电路图案。

公开(公告)号：US20090301766A1

公开(公告)日：2009-12-10

申请号：US12219441

申请日：2008-07-22

申请人： Hwa Sun Park ,  Yul Kyo Chung ,  Jin Won Lee ,  Jin Soo Jeong

发明人： Hwa Sun Park ,  Yul Kyo Chung ,  Jin Won Lee ,  Jin Soo Jeong

IPC分类号： H05K1/03 ,  H01R43/00

CPC分类号： H05K1/185 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K3/4602 ,  H05K2201/0394 ,  H05K2201/10674 ,  H05K2201/10969 ,  Y10T29/49171

摘要： Disclosed herein is a printed circuit board including an electronic component embedded therein, as the electronic component is supported on the metal layer of core substrate, thus supporting and radiation performances are improved, production costs are reduced, and the manufacturing process is simplified.

摘要翻译： 这里公开了包括嵌入其中的电子部件的印刷电路板，由于电子部件被支撑在芯基板的金属层上，因此支撑和辐射性能得到改善，生产成本降低，并且制造过程简化。

公开(公告)号：US07037739B2

公开(公告)日：2006-05-02

申请号：US10751858

申请日：2004-01-06

申请人： Young Tae Byun ,  Hwa Sun Park ,  Seok Lee ,  Deok Ha Woo ,  Jong Chang Yi

发明人： Young Tae Byun ,  Hwa Sun Park ,  Seok Lee ,  Deok Ha Woo ,  Jong Chang Yi

IPC分类号： H01L21/00

CPC分类号： G02F1/025 ,  G02F2001/0152 ,  G02F2001/0154 ,  G02F2202/102 ,  G02F2203/50

摘要： A fabrication method of an epilayer structure for InGaAsP/InP ridge waveguide phase modulator with high phase modulation efficiency. It relates to a P-p-n-N InGaAsP/InP ridge waveguide phase modulator fabricated to be that the phase change of the TE-mode is linearly proportional to the reverse bias voltage at 1.55 μm wavelength. A method for fabricating an epilayer structure for achieving the optical confinement in the vertical direction of an InGaAsP/InP waveguide phase modulator, characterized by comprising the steps of: forming a first cladding layer of N-InP on an N+-InP substrate; forming a first waveguide layer of n-InGaAsP and a second waveguide layer of p-InGaAsP in sequence on the first cladding layer; forming a second cladding layer of P-InP and a third cladding layer of P-InP in sequence on the second waveguide layer; and forming an electrode layer of p+InGaAs on the third cladding layer.

摘要翻译： 具有高相位调制效率的InGaAsP / InP脊波导相位调制器的外延层结构的制造方法。 它涉及一种P-p-n-N InGaAsP / InP脊波导相位调制器，其制造为TE模式的相变与1.55mum波长处的反偏压成线性比例。 一种用于制造用于实现InGaAsP / InP波导相位调制器的垂直方向上的光限制的外延层结构的方法，其特征在于包括以下步骤：在N + 1上形成N-InP的第一包层， SUP> -InP底物; 在第一包层上依次形成n-InGaAsP的第一波导层和p-InGaAsP的第二波导层; 在第二波导层上依次形成P-InP的第二包层和P-InP的第三包层; 以及在所述第三覆层上形成p + + InGaAs的电极层。

公开(公告)号：US09000593B2

公开(公告)日：2015-04-07

申请号：US13568208

申请日：2012-08-07

申请人： Su Jeong Suh ,  Hwa Sun Park ,  Hyeong Chul Youn

发明人： Su Jeong Suh ,  Hwa Sun Park ,  Hyeong Chul Youn

IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L23/495 ,  H01L23/14 ,  H01L33/64

CPC分类号： H01L33/647 ,  H01L23/142 ,  H01L23/49562 ,  H01L33/64 ,  H01L33/641 ,  H01L33/642 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/4918 ,  H01L2933/0066 ,  H01L2933/0075 ,  H01L2924/00014

摘要： A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal line is electrically connected to a second electrode of the semiconductor device and spaced apart from the first metal line. The metal support part is disposed between the first metal line and the second metal line. The first insulating part is disposed between the first metal line and the metal support part and configured to electrically insulate the first metal line from the metal support part. The second insulating part is disposed between the second metal line and the metal support part and configured to electrically insulate the second metal line from the metal support part.

公开(公告)号：US20130037955A1

公开(公告)日：2013-02-14

申请号：US13568208

申请日：2012-08-07

申请人： Su Jeong SUH ,  Hwa Sun Park ,  Hyeong Chul Youn

发明人： Su Jeong SUH ,  Hwa Sun Park ,  Hyeong Chul Youn

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L33/647 ,  H01L23/142 ,  H01L23/49562 ,  H01L33/64 ,  H01L33/641 ,  H01L33/642 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/4918 ,  H01L2933/0066 ,  H01L2933/0075 ,  H01L2924/00014

摘要： A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal line is electrically connected to a second electrode of the semiconductor device and spaced apart from the first metal line. The metal support part is disposed between the first metal line and the second metal line. The first insulating part is disposed between the first metal line and the metal support part and configured to electrically insulate the first metal line from the metal support part. The second insulating part is disposed between the second metal line and the metal support part and configured to electrically insulate the second metal line from the metal support part.

公开(公告)号：US07328504B2

公开(公告)日：2008-02-12

申请号：US11453790

申请日：2006-06-15

申请人： Seung Gu Kim ,  Chang Sup Ryu ,  Han Seo Cho ,  Doo Hwan Lee ,  Hwa Sun Park

发明人： Seung Gu Kim ,  Chang Sup Ryu ,  Han Seo Cho ,  Doo Hwan Lee ,  Hwa Sun Park

IPC分类号： H05K3/30 ,  H05K3/34 ,  H01K3/10

CPC分类号： H05K1/188 ,  H05K1/185 ,  H05K2201/0355 ,  H05K2201/10674 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

摘要： Disclosed is a method for manufacturing a circuit board, comprising step for preparing an insulating member and an electronic component having position-setting means on the lower surface thereof (S110), step for forming mounting holes in the insulating member (S120), step for mounting the electronic component on the insulating member to meet the position-setting means and the mounting holes (S130), step for forming copper cladding coated with an adhesive on the insulating member (S140), step for applying heat and/or pressure to the copper cladding (S150), and step for forming a via-hole in the copper cladding to be electrically connected to the electronic component, and step for forming a circuit pattern in the copper cladding (S160). The step (S150) can comprise a step (S240) for applying inter-adhesive on respective surfaces of the insulating member, and a step (S250) for applying copper cladding on respective surfaces of the inter-adhesive.

摘要翻译： 公开了一种制造电路板的方法，包括在其下表面上制备绝缘构件和具有位置设定装置的电子部件的步骤（S110），用于在绝缘构件中形成安装孔的步骤（S120）， 步骤，用于将所述电子部件安装在所述绝缘部件上以满足所述位置设定装置和所述安装孔（S130），用于在所述绝缘部件上形成涂覆有粘合剂的铜包层的步骤（S140），用于施加热和/ 或对铜包层的压力（S150），以及用于在铜包层中形成电气连接到电子部件的通孔的步骤，以及用于在铜包层中形成电路图案的步骤（S160）。 步骤（S150）可以包括用于在绝缘构件的相应表面上施加粘合剂的步骤（S 240），以及用于在粘合剂的各个表面上施加铜包层的台阶（S 250）。