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公开(公告)号：US20130299218A1
公开(公告)日：2013-11-14
申请号：US13936420
申请日：2013-07-08
Applicant: IBIDEN CO., LTD.
Inventor： Yasushi INAGAKI , Katsuyuki Sano
IPC: H05K1/09
CPC classification number: H05K1/09 , H01L23/49816 , H01L23/49822 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/15312 , H01L2924/19106 , H01L2924/3011 , H01L2924/3511 , H05K1/0237 , H05K1/056 , H05K1/183 , H05K1/185 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4641 , H05K2201/0347 , H05K2201/0352 , H05K2201/09309 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09809 , H01L2224/05599
Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.
Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。
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公开(公告)号：US20130206466A1
公开(公告)日：2013-08-15
申请号：US13835505
申请日：2013-03-15
Applicant: IBIDEN CO., LTD.
Inventor： Yasushi Inagaki , Katsuyuki Sano
CPC classification number: H05K1/0237 , H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L23/5383 , H01L23/66 , H01L24/81 , H01L2223/6616 , H01L2223/6622 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13111 , H01L2224/16225 , H01L2224/81192 , H01L2224/81801 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/15787 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H01L2924/3511 , H05K1/0224 , H05K1/0263 , H05K1/0265 , H05K1/111 , H05K1/115 , H05K1/144 , H05K1/185 , H05K3/4602 , H05K2201/0352 , H05K2201/09309 , H05K2201/09536 , H05K2201/09736 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A multilayer printed wiring board includes a core substrate having a through-hole formed through the substrate, an interlayer insulation layer formed on the substrate and having a via conductor formed through the insulation layer, and a conductor layer formed on the insulation layer and connected to the via in the insulation layer. The substrate has multiplayer insulation structure, outer power layer formed on surface of the structure, outer ground layer formed on opposite surface of the structure, inner power layer formed inside the structure and inner ground layer formed inside the structure, each of the inner layers has tapered end having angle satisfying 2.8
Abstract translation: 多层印刷电路板包括具有通过基板形成的通孔的芯基板，形成在基板上并具有通过绝缘层形成的通孔导体的层间绝缘层，以及形成在绝缘层上的导体层， 绝缘层中的通孔。 所述基板具有多层绝缘结构，在所述结构的表面上形成的外层电力层，在所述结构的相对面上形成的外部地层，在所述结构内形成的内部电力层和在所述结构内形成的内部地层， 具有满足2.8
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Patent Agency Ranking
公开(公告)号：US09226397B2
公开(公告)日：2015-12-29
申请号：US13936420
申请日：2013-07-08
Applicant: IBIDEN CO., LTD.
Inventor： Yasushi Inagaki , Katsuyuki Sano
CPC classification number: H05K1/09 , H01L23/49816 , H01L23/49822 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/15312 , H01L2924/19106 , H01L2924/3011 , H01L2924/3511 , H05K1/0237 , H05K1/056 , H05K1/183 , H05K1/185 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4641 , H05K2201/0347 , H05K2201/0352 , H05K2201/09309 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09809 , H01L2224/05599
Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.
Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为具有15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。
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公开(公告)号：US09101054B2
公开(公告)日：2015-08-04
申请号：US13835505
申请日：2013-03-15
Applicant: IBIDEN CO., LTD.
Inventor： Yasushi Inagaki , Katsuyuki Sano
IPC: H05K1/11 , H05K1/02 , H01L21/48 , H01L23/498 , H01L23/50 , H01L23/538 , H01L23/66 , H01L23/00 , H05K3/46 , H05K1/14 , H05K1/18
CPC classification number: H05K1/0237 , H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L23/5383 , H01L23/66 , H01L24/81 , H01L2223/6616 , H01L2223/6622 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13111 , H01L2224/16225 , H01L2224/81192 , H01L2224/81801 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/15787 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H01L2924/3511 , H05K1/0224 , H05K1/0263 , H05K1/0265 , H05K1/111 , H05K1/115 , H05K1/144 , H05K1/185 , H05K3/4602 , H05K2201/0352 , H05K2201/09309 , H05K2201/09536 , H05K2201/09736 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A multilayer printed wiring board includes a core substrate having a through-hole formed through the substrate, an interlayer insulation layer formed on the substrate and having a via conductor formed through the insulation layer, and a conductor layer formed on the insulation layer and connected to the via in the insulation layer. The substrate has multiplayer insulation structure, outer power layer formed on surface of the structure, outer ground layer formed on opposite surface of the structure, inner power layer formed inside the structure and inner ground layer formed inside the structure, each of the inner layers has tapered end having angle satisfying 2.8
Abstract translation: 多层印刷电路板包括具有通过基板形成的通孔的芯基板，形成在基板上并具有通过绝缘层形成的通孔导体的层间绝缘层，以及形成在绝缘层上的导体层， 绝缘层中的通孔。 所述基板具有多层绝缘结构，在所述结构的表面上形成的外层电力层，在所述结构的相对面上形成的外部地层，在所述结构内形成的内部电力层和在所述结构内形成的内部地层， 锥形端部具有满足2.8
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公开(公告)号：US11792937B2
公开(公告)日：2023-10-17
申请号：US17469124
申请日：2021-09-08
Applicant: IBIDEN CO., LTD.
Inventor： Takahiro Yamada , Seiji Izawa , Katsuyuki Sano
CPC classification number: H05K1/183 , H05K1/113 , H05K1/185 , H05K2201/096
Abstract: A component built-in wiring substrate includes a first insulating layer, a first conductor layer formed on a first surface of the first insulating layer and including a component mounting pad, a second conductor layer formed on a second surface of the first insulating layer on the opposite side with respect to the first surface, via conductors formed in the first insulating layer such that the via conductors are connecting the second conductor layer and the component mounting pad of the first conductor layer, a second insulating layer formed on the first insulating layer and having a component accommodating portion penetrating through the second insulating layer such that the component mounting pad is positioned at bottom of the accommodating portion, and an electronic component positioned in the accommodating portion of the second insulating layer such that the electronic component is mounted on the component mounting pad of the first conductor layer.
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公开(公告)号：US11749596B2
公开(公告)日：2023-09-05
申请号：US17452123
申请日：2021-10-25
Applicant: IBIDEN CO., LTD.
Inventor： Katsuyuki Sano , Yoji Sawada
IPC: H01L21/48 , H01L23/498
CPC classification number: H01L23/49838 , H01L21/486 , H01L21/4857 , H01L23/49811 , H01L23/49822
Abstract: A wiring substrate includes a conductor pad, an insulating layer formed on the conductor pad such that the insulating layer is covering the conductor pad and has a through hole, a bump formed on the conductor pad such that the bump is formed in the through hole penetrating through the insulating layer. The conductor pad is formed such that the conductor pad has a connecting surface connected to the bump, a concave part formed on the connecting surface of the conductor pad to the bump, and a convex part formed in the concave part.
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公开(公告)号：US20130248234A1
公开(公告)日：2013-09-26
申请号：US13872650
申请日：2013-04-29
Applicant: IBIDEN CO., LTD.
Inventor： Yasushi Inagaki , Katsuyuki Sano
IPC: H05K1/18
CPC classification number: H05K1/09 , H01L23/49816 , H01L23/49822 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/15312 , H01L2924/19106 , H01L2924/3011 , H01L2924/3511 , H05K1/0237 , H05K1/056 , H05K1/183 , H05K1/185 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4641 , H05K2201/0347 , H05K2201/0352 , H05K2201/09309 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09809 , H01L2224/05599
Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.
Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。
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