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公开(公告)号：US20200315012A1
公开(公告)日：2020-10-01
申请号：US16828050
申请日：2020-03-24
Applicant: IBIDEN CO., LTD.
Inventor： Takenobu NAKAMURA , Takahiro YAMAZAKI , Takashi YAMAUCHI , Toshihide MAKINO
Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer, and the first and second laminated structures are formed such that a surface of the second laminated structure on a side away from the core layer has unevenness smaller than unevenness of a surface of the first laminated structure on a side away from the core layer.
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公开(公告)号：US20200315009A1
公开(公告)日：2020-10-01
申请号：US16830507
申请日：2020-03-26
Applicant: IBIDEN CO., LTD.
Inventor： Takenobu NAKAMURA , Takahiro YAMAZAKI , Takashi YAMAUCHI , Toshihide MAKINO
Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate layers, second conductor layers including second inner, outer and intermediate layers, interlayer insulating layers interposed between the first conductor layers and between the second conductor layers, and via conductors formed in the insulating layers such that each via conductor connects two conductor layers and is integrally formed with one of the conductor layers on side away from the core layer. The first and/or second inner conductor layers has a first conductor layer structure including metal foil and plating film layers, the first and/or second outer conductor layers has the first structure, the first and/or second intermediate conductor layers has a second conductor layer structure including metal foil and plating film layers, and the via conductors include a group integrally formed with the first structure and including constricted via conductors each having a constricted portion.
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公开(公告)号：US20200296841A1
公开(公告)日：2020-09-17
申请号：US16887443
申请日：2020-05-29
Applicant: IBIDEN CO., LTD.
Inventor： Toshihide MAKINO , Hidetoshi NOGUCHI
Abstract: A wiring board includes core substrate, a first build-up layer on first surface of the substrate and including conductive and insulating resin layers, and a second build-up layer on second surface of the substrate and including conductive and insulating resin layers. The first build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of a conductive layer on a non-outermost resin layer, and the second build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of a conductive layer on a non-outermost resin layer.
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公开(公告)号：US20200315011A1
公开(公告)日：2020-10-01
申请号：US16827887
申请日：2020-03-24
Applicant: IBIDEN CO., LTD
Inventor： Takenobu NAKAMURA , Takahiro YAMAZAKI , Takashi YAMAUCHI , Toshihide MAKINO
Abstract: A wiring substrate includes a core layer, first conductor layers including a first inner conductor layer, a first outer conductor layer and a first intermediate conductor layer, second conductor layers including a second inner conductor layer, a second outer conductor layer and a second intermediate conductor layer, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, and the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer and includes a conductor pattern formed such that an upper surface of the conductor pattern has an edge portion forming an inclined portion inclined toward the core layer.
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公开(公告)号：US20190215959A1
公开(公告)日：2019-07-11
申请号：US16245396
申请日：2019-01-11
Applicant: IBIDEN CO., LTD.
Inventor： Takema ADACHI , Toshihide MAKINO , Hidetoshi NOGUCHI
CPC classification number: H05K1/116 , H05K1/113 , H05K3/4015 , H05K3/4655 , H05K3/4688
Abstract: A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. The core substrate includes a core layer, through-hole conductors and through-hole lands. Metal foils of the through-hole lands in the core substrate have mat surfaces at interfaces of the core layer in the core substrate, metal foils of via lands in the build-up layers have inner mat surfaces at interfaces of insulating layers, and metal foils of outermost conductor layers in the build-up layers have outermost mat surfaces at interfaces of outermost insulating layers. Ten-point average roughness (RzI1) of the inner first mat surface is smaller than each of ten-point average roughness (Rz1, Rz2) of the mat surfaces and ten-point average roughness (RzO1, RzO2) of the outermost mat surfaces. Ten-point average roughness (RzI2) of the inner second mat surface is smaller than each of the ten-point average roughness (Rz1, Rz2, RzO1, RzO2).
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Patent Agency Ranking
公开(公告)号：US20190124767A1
公开(公告)日：2019-04-25
申请号：US16169340
申请日：2018-10-24
Applicant: IBIDEN CO., LTD.
Inventor： Takema ADACHI , Toshihide MAKINO , Hidetoshi NOGUCHI
CPC classification number: H05K1/115 , H05K1/0373 , H05K3/06 , H05K3/422 , H05K3/4644 , H05K3/4652 , H05K2201/09227 , H05K2201/09563 , H05K2201/096 , H05K2201/09727 , H05K2201/09827 , H05K2201/099 , H05K2203/072 , H05K2203/107 , H05K2203/1572
Abstract: A printed wiring board includes: a core substrate having a core layer, first and second conductor layers, and through-hole conductors penetrating through the core layer and connecting the conductor layers; and first and second build-up layers each including an insulating layer, an inner side conductor layer, an outermost insulating layer, an outermost conductor layer, and a solder resist layer. Each of the conductor layers includes conductor circuits having substantially a trapezoid cross-sectional shape, and spaces between adjacent conductor circuits, and includes a metal foil, a seed layer, and an electrolytic plating film. The inner side conductor layers have the smallest minimum circuit width, the smallest minimum space width and the largest base angle among the conductor layers. The insulating layers have the smallest ten-point average roughness rz3, rz7 among the ten-point average roughness rz3, rz7, rz1, rz2, rz5 and rz9 of the core layer, insulating layers and outermost insulating layers.
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公开(公告)号：US20200315013A1
公开(公告)日：2020-10-01
申请号：US16829675
申请日：2020-03-25
Applicant: IBIDEN CO., LTD.
Inventor： Takenobu NAKAMURA , Takahiro YAMAZAKI , Takashi YAMAUCHI , Toshihide MAKINO
Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including metal foil and plating film layers and includes first conductor pattern having a side surface curved toward inner side of the first pattern, the first and/or second outer conductor layers has the first laminated structure and includes the first conductor pattern having the side surface curved toward the inner side of the first pattern, and the first and/or second intermediate conductor layers has a second laminated structure including metal foil and plating film layers and includes second conductor pattern having a side surface curved toward outer side of the second pattern.
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公开(公告)号：US20190124768A1
公开(公告)日：2019-04-25
申请号：US16167850
申请日：2018-10-23
Applicant: IBIDEN CO., LTD.
Inventor： Takema ADACHI , Toshihide MAKINO , Hidetoshi NOGUCHI
Abstract: A printed wiring board includes a core substrate and first and second build-up layers. The substrate includes a core layer, through-hole conductors formed in through holes such that each through hole has first opening tapering from first toward second surface of the core layer, and second opening tapering from second toward first surface of the core layer, and first and second through-hole lands directly connected to the through-hole conductors. Each build-up layer includes an insulating layer, via conductors, via lands, an outermost insulating layer, an outermost conductor layer, and outermost via conductors. Each of the through-hole lands, via lands and outermost conductor layers includes a metal foil, a seed layer and an electrolytic plating film. The foils have mat surfaces such that the mat surfaces of the via lands has ten-point average roughness smaller than ten-point average roughness of the mat surfaces of the through-hole lands and outermost conductor layers.
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公开(公告)号：US20180042124A1
公开(公告)日：2018-02-08
申请号：US15671451
申请日：2017-08-08
Applicant: IBIDEN CO., LTD.
Inventor： Toshihide MAKINO , Hidetoshi Noguchi
CPC classification number: H05K3/4652 , H05K1/0366 , H05K1/11 , H05K1/111 , H05K1/115 , H05K1/116 , H05K1/16 , H05K3/061 , H05K3/202 , H05K3/429 , H05K3/4602 , H05K3/4655 , H05K2201/09009 , H05K2201/096
Abstract: A wiring board includes core substrate, a first build-up layer on first surface of the substrate and including conductive and insulating resin layers, and a second build-up layer on second surface of the substrate and including conductive and insulating resin layers. The first build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of each conductive layer on a non-outermost resin layer, and the second build-up is foimed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of each conductive layer on a non-outermost resin layer.
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公开(公告)号：US20150257276A1
公开(公告)日：2015-09-10
申请号：US14633241
申请日：2015-02-27
Applicant: IBIDEN CO., LTD.
Inventor： Toshihide MAKINO
CPC classification number: H05K3/0052 , H05K3/0047 , H05K3/403 , H05K2203/0228 , Y10T29/49124
Abstract: A method for manufacturing a wiring board includes preparing a large-sized wiring board having an effective region and a dummy region such that the board has a penetrating hole on a border of the effective and dummy regions and an inner-hole conductive layer covering an inner surface of the penetrating hole, moving a rotary tool having a tip blade along rotation axis at a peripheral portion of the penetrating hole such that the rotary tool drills a hole into the board at the peripheral portion and segments the conductive layer into portions in the effective and dummy regions, and moving a rotary tool having a side blade in a direction perpendicular to rotation axis such that the dummy region is cut off from the effective region after the rotary tool having tip blade makes the hole and a wiring board having the effective region of the board is formed.
Abstract translation: 一种布线基板的制造方法，其特征在于，准备具有有效区域和虚设区域的大型布线基板，使得所述基板在有效区域和虚设区域的边界上具有贯通孔，以及覆盖内部 所述贯通孔的表面在所述贯通孔的周缘部沿着旋转轴移动具有尖端刀片的旋转工具，使得所述旋转工具在所述周边部分向所述板钻一孔，并将所述导电层分割成有效的部分 和虚拟区域，并且使具有侧叶片的旋转工具沿垂直于旋转轴线的方向移动，使得在具有尖端刀片的旋转工具形成该孔之后，虚拟区域与有效区域切断，并且具有有效区域的布线板 的董事会成立。
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