公开(公告)号：US20130134572A1

公开(公告)日：2013-05-30

申请号：US13749006

申请日：2013-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Lenniger ,  Andre Uhlemann ,  Olaf Hohlfeld

IPC: H01L23/367 ,  H01L21/50

CPC classification number: H01L23/367 ,  H01L21/50 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48132 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/85205 ,  H01L2224/8584 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.

Abstract translation: 半导体器件包括与衬底连接的半导体芯片和与衬底接合的基板。 基板包括包覆到第二金属层的第一金属层。 第二金属层变形以提供销鳍或翅片冷却结构。 第二金属层具有没有引脚而没有引脚鳍的子层。 第一金属层具有第一厚度，并且子层具有第二厚度。 第一厚度与第二厚度之比至少为4:1。

公开(公告)号：US20240098389A1

公开(公告)日：2024-03-21

申请号：US18524008

申请日：2023-11-30

Applicant: Infineon Technologies AG

Inventor： Wolfgang Budde ,  Jens de Bock ,  Daniel Domes ,  Andreas Lenniger ,  Bjoern Rentemeister ,  Stefan Hubert Schmies ,  Andreas Vetter

IPC: H04Q9/00

CPC classification number: H04Q9/00 ,  H04Q2209/10 ,  H04Q2209/84

Abstract: An electronic device includes an interface configured to receive telemetry information for one or more power semiconductor devices and a data acquisition and processing unit. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a current slew rate that exceeds a predetermined level as determined by the telemetry information. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a temperature that exceeds a predetermined level as determined by the telemetry information. An electronic system that includes the electronic device is also described.

公开(公告)号：US08963321B2

公开(公告)日：2015-02-24

申请号：US13749006

申请日：2013-01-24

Applicant: Infineon Technologies AG

Inventor： Andreas Lenniger ,  Andre Uhlemann ,  Olaf Hohlfeld

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L21/00 ,  H01L23/367 ,  H01L21/50 ,  H01L23/473 ,  H01L23/00 ,  H01L25/07 ,  H01L23/24 ,  H01L23/373 ,  H01L23/31 ,  H01L23/40

CPC classification number: H01L23/367 ,  H01L21/50 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48132 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/85205 ,  H01L2224/8584 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.

Abstract translation: 半导体器件包括与衬底连接的半导体芯片和与衬底接合的基板。 基板包括包覆到第二金属层的第一金属层。 第二金属层变形以提供销鳍或翅片冷却结构。 第二金属层具有没有引脚而没有引脚鳍的子层。 第一金属层具有第一厚度，并且子层具有第二厚度。 第一厚度与第二厚度之比至少为4:1。

公开(公告)号：US11889246B1

公开(公告)日：2024-01-30

申请号：US17857615

申请日：2022-07-05

Applicant: Infineon Technologies AG

Inventor： Wolfgang Budde ,  Jens de Bock ,  Daniel Domes ,  Andreas Lenniger ,  Bjoern Rentemeister ,  Stefan Hubert Schmies ,  Andreas Vetter

IPC: H04Q9/00

CPC classification number: H04Q9/00 ,  H04Q2209/10 ,  H04Q2209/84

Abstract: An electronic device includes: an interface configured to receive telemetry information for one or more power semiconductor devices; and a data acquisition and processing unit. The data acquisition and processing unit may be configured to periodically update an estimate of a remaining lifetime of the one or more power semiconductor devices, based on the telemetry information collected during use of the one or more power semiconductor devices and received at the interface. The data acquisition and processing unit may be configured to adjust one or more operating parameters for each of the one or more power semiconductor devices that has reached a predetermined level of degradation as determined by the telemetry information. An electronic system that includes the electronic device is also described.

公开(公告)号：US20240015417A1

公开(公告)日：2024-01-11

申请号：US17857615

申请日：2022-07-05

Applicant: Infineon Technologies AG

Inventor： Wolfgang Budde ,  Jens de Bock ,  Daniel Domes ,  Andreas Lenniger ,  Bjoern Rentemeister ,  Stefan Hubert Schmies ,  Andreas Vetter

IPC: H04Q9/00

CPC classification number: H04Q9/00 ,  H04Q2209/84 ,  H04Q2209/10

Abstract: An electronic device includes: an interface configured to receive telemetry information for one or more power semiconductor devices; and a data acquisition and processing unit. The data acquisition and processing unit may be configured to periodically update an estimate of a remaining lifetime of the one or more power semiconductor devices, based on the telemetry information collected during use of the one or more power semiconductor devices and received at the interface. The data acquisition and processing unit may be configured to adjust one or more operating parameters for each of the one or more power semiconductor devices that has reached a predetermined level of degradation as determined by the telemetry information. An electronic system that includes the electronic device is also described.