公开(公告)号：US11955450B2

公开(公告)日：2024-04-09

申请号：US18142109

申请日：2023-05-02

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld

IPC: H01L23/00 ,  H01L27/12

CPC classification number: H01L24/34 ,  H01L27/1248 ,  H01L2224/32013 ,  H01L2224/32054 ,  H01L2224/32055 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32113 ,  H01L2224/32258 ,  H01L2224/49175

Abstract: A method for producing a semiconductor arrangement includes: forming a first metallization layer on a first side of a dielectric insulation layer, the first metallization layer having at least two sections, each section being separated from a neighboring section by a recess; arranging a semiconductor body on one of the sections of the first metallization layer; and forming at least one indentation between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.

公开(公告)号：US20210398821A1

公开(公告)日：2021-12-23

申请号：US17342975

申请日：2021-06-09

Applicant: Infineon Technologies AG

Inventor： Fabian Craes ,  Carsten Ehlers ,  Olaf Hohlfeld ,  Ulrich Wilke

IPC: H01L21/54 ,  H01L21/48 ,  H01L21/56 ,  H01L21/308 ,  H01L21/67 ,  H01L23/00

Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.

公开(公告)号：US20200321262A1

公开(公告)日：2020-10-08

申请号：US16839683

申请日：2020-04-03

Applicant: Infineon Technologies AG

Inventor： Christian Schweikert ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Waldemar Jakobi

IPC: H01L23/367 ,  G01K1/14 ,  H01L21/48

Abstract: A power semiconductor module includes a power semiconductor chip arranged between a first substrate and a second substrate and electrically coupled to the substrates, and a temperature sensor arranged between the substrates and laterally besides the power semiconductor chip such that a first side of the temperature sensor faces the first substrate and a second side of the temperature sensor faces the second substrate. A first electrical contact of the temperature sensor is arranged on the first side and electrically coupled to the first substrate. A second electrical contact of the temperature sensor is arranged on the second side and electrically coupled to the second substrate.

公开(公告)号：US09984928B2

公开(公告)日：2018-05-29

申请号：US15378669

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Peter Kanschat

IPC: H01L21/44 ,  H01L21/78 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

公开(公告)号：US09972596B2

公开(公告)日：2018-05-15

申请号：US14926615

申请日：2015-10-29

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/72 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/3736 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: One aspect of the invention relates to a chip assemblage. The latter comprises a number of semiconductor chips, each of which has a semiconductor body having an underside, and also a top side, which is spaced apart from the underside in a vertical direction. A top main electrode is arranged on the top side and a bottom main electrode is arranged on the underside. Moreover, each of the semiconductor chips has a control electrode, by means of which an electric current between the top main electrode and the bottom main electrode can be controlled. The semiconductor chips are connected to one another by a dielectric embedding compound to form a solid assemblage. The chip assemblage additionally comprises a common control terminal, and a common reference potential terminal. The common control terminal is electrically conductively connected to each of the control electrodes via a control electrode interconnection structure, and the common reference potential terminal is electrically conductively connected to each of the first main electrodes via a main electrode interconnection structure. Moreover, a dedicated, electrically conductive top compensation lamina is present for each of the semiconductor chips, said top compensation lamina being arranged on that side of the top main electrode which faces away from the semiconductor body and being cohesively and electrically conductively connected to the top main electrode.

公开(公告)号：US09818730B2

公开(公告)日：2017-11-14

申请号：US14477386

申请日：2014-09-04

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/48 ,  H01L25/07 ,  H01L23/492 ,  H01L23/495 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/051 ,  H01L23/31

CPC classification number: H01L25/072 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

公开(公告)号：US20170098580A1

公开(公告)日：2017-04-06

申请号：US15378669

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Peter Kanschat

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L21/66

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

公开(公告)号：US09524951B2

公开(公告)日：2016-12-20

申请号：US14669208

申请日：2015-03-26

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld

IPC: H01L25/065 ,  H01L23/10 ,  H01L23/492 ,  H01L23/04 ,  H01L23/31 ,  H01L23/48 ,  H01L25/07 ,  H01L23/051

CPC classification number: H01L25/0655 ,  H01L23/04 ,  H01L23/051 ,  H01L23/10 ,  H01L23/3142 ,  H01L23/48 ,  H01L23/492 ,  H01L24/96 ,  H01L25/07 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor assembly includes a frame having at least one opening, an identical number of electrically conductive first contact plates, and an identical number of chip arrays. Each chip array has a number of semiconductor chips that are cohesively connected to one another by an embedding compound. In addition, each of the semiconductor chips has a first load terminal and a second load terminal arranged at mutually opposite sides of the relevant semiconductor chip. One of the chip arrays is inserted into each of the openings. Each of the first contact plates is arranged above one of the chip arrays in such a way that, for each of the semiconductor chips, the first load terminal is situated at a side of said semiconductor chip facing the first contact plate and the second load terminal is situated a of said semiconductor chip facing away from the first contact plate.

Abstract translation: 半导体组件包括具有至少一个开口，相同数量的导电第一接触板和相同数量的芯片阵列的框架。 每个芯片阵列具有通过嵌入化合物彼此内聚连接的多个半导体芯片。 此外，每个半导体芯片具有布置在相关半导体芯片的相对的相对侧的第一负载端子和第二负载端子。 其中一个芯片阵列插入到每个开口中。 每个第一接触板被布置在一个芯片阵列之上，使得对于每个半导体芯片，第一负载端子位于面向第一接触板的第一半导体芯片的一侧和第二负载端子 位于所述半导体芯片的背离第一接触板的一侧。

公开(公告)号：US20150130071A1

公开(公告)日：2015-05-14

申请号：US14077696

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Angela Kessler ,  Magdalena Hoier

IPC: H01L25/07 ,  H01L23/31 ,  H01L25/00 ,  H01L23/522

CPC classification number: H01L25/074 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3135 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.

Abstract translation: 半导体封装包括包括多个半导体晶体管芯片的第一半导体模块和设置在半导体晶体管芯片上方的第一封装层，以及设置在第一半导体模块上方的第二半导体模块。 第二半导体模块包括多个半导体驱动器通道和设置在半导体驱动器通道上方的第二封装层。 半导体驱动器通道被配置为驱动半导体晶体管芯片。

公开(公告)号：US20150092380A1

公开(公告)日：2015-04-02

申请号：US14500041

申请日：2014-09-29

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld

IPC: H05K1/11 ,  H05K3/10 ,  H05K3/32 ,  H05K1/18

CPC classification number: H05K1/11 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K1/141 ,  H05K1/181 ,  H05K1/184 ,  H05K3/0061 ,  H05K3/10 ,  H05K3/32 ,  H05K3/368 ,  H05K3/4092 ,  H05K3/4697 ,  H05K2201/10409 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor module includes a printed circuit board, a ceramic substrate and a semiconductor chip. The printed circuit board includes an insulating material, a cutout formed in the insulating material, and a first metallization layer, which is partly embedded into the insulating material. The first metallization layer includes a conductor track projection projecting into the cutout. The ceramic substrate includes a dielectric, ceramic insulation carrier, and an upper substrate metallization applied to a top side of the insulation carrier. The semiconductor chip is arranged on the upper substrate metallization, and the first metallization layer is mechanically and electrically conductively connected to the upper substrate metallization at the conductor track projection.

Abstract translation: 半导体模块包括印刷电路板，陶瓷基板和半导体芯片。 印刷电路板包括绝缘材料，形成在绝缘材料中的切口以及部分地嵌入绝缘材料中的第一金属化层。 第一金属化层包括突出到切口中的导体轨道突起。 陶瓷基板包括电介质，陶瓷绝缘载体和施加到绝缘载体的顶侧的上基板金属化。 半导体芯片布置在上基板金属化上，并且第一金属化层在导体轨道突起处机械地和导电地连接到上基板金属化。