公开(公告)号：US12060266B2

公开(公告)日：2024-08-13

申请号：US17248799

申请日：2021-02-08

Applicant: Infineon Technologies AG

Inventor： Andre Brockmeier ,  Markus Bergmeister ,  Bernhard Goller ,  Daniel Pieber ,  Sokratis Sgouridis

IPC: B81C1/00

CPC classification number: B81C1/00896 ,  B81C1/00047 ,  B81C1/00119 ,  B81C2201/053

Abstract: A method for producing MEMS components comprises generating a carrier having a plurality of recesses. An adhesive structure is arranged on the carrier and in the recesses. A semiconductor wafer is generated, which has a plurality of MEMS structures arranged at the first main surface of the semiconductor wafer. The adhesive structure is attached to the first main surface of the semiconductor wafer, with the recesses being arranged above the MEMS structures and the adhesive structure not contacting the MEMS structures. The semiconductor wafer is singulated into a plurality of MEMS components by applying a mechanical dicing process.

公开(公告)号：US20240006218A1

公开(公告)日：2024-01-04

申请号：US18211656

申请日：2023-06-20

Applicant: Infineon Technologies AG

Inventor： Gregor Langer ,  Bernhard Goller ,  Nilesha Mishra ,  Matteo Piccin ,  Franz-Josef Pichler

IPC: H01L21/683 ,  H01L21/66 ,  H01L21/304

CPC classification number: H01L21/6835 ,  H01L22/14 ,  H01L21/3043 ,  H01L2221/68318 ,  H01L2221/68381

Abstract: A method of manufacturing a semiconductor device in a semiconductor body is proposed. The method includes processing a semiconductor body at a first surface of the semiconductor body. The method further includes attaching the semiconductor body to a carrier via the first surface. The carrier includes an inner part and an outer part at least partly surrounding the inner part. The method further includes processing the semiconductor body at a second surface opposite to the first surface. The method further includes detaching the inner part of the carrier from the semiconductor body.

公开(公告)号：US20230127556A1

公开(公告)日：2023-04-27

申请号：US17743006

申请日：2022-05-12

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Alexander Binter ,  Tobias Hoechbauer ,  Martin Huber ,  Iris Moder ,  Matteo Piccin ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/288 ,  H01L21/78

Abstract: A method of processing a semiconductor wafer includes: forming one or more epitaxial layers over a first main surface of the semiconductor wafer; forming one or more porous layers in the semiconductor wafer or in the one or more epitaxial layers, wherein the semiconductor wafer, the one or more epitaxial layers and the one or more porous layers collectively form a substrate; forming doped regions of a semiconductor device in the one or more epitaxial layers; and after forming the doped regions of the semiconductor device, separating a non-porous part of the semiconductor wafer from a remainder of the substrate along the one or more porous layers.

公开(公告)号：US11476111B2

公开(公告)日：2022-10-18

申请号：US16811192

申请日：2020-03-06

Applicant: Infineon Technologies AG

Inventor： Iris Moder ,  Bernhard Goller ,  Tobias Franz Wolfgang Hoechbauer ,  Roland Rupp ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/475 ,  H01L21/467

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US20200168449A1

公开(公告)日：2020-05-28

申请号：US16677801

申请日：2019-11-08

Applicant: Infineon Technologies AG

Inventor： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/02 ,  H01L21/465 ,  H01L21/8258

Abstract: A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.

公开(公告)号：US10157765B2

公开(公告)日：2018-12-18

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/283 ,  H01L21/78 ,  H01L21/033 ,  H01L21/285 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

公开(公告)号：US09886660B2

公开(公告)日：2018-02-06

申请号：US15344191

申请日：2016-11-04

Applicant: Infineon Technologies AG

Inventor： Dirk Hammerschmidt ,  Bernhard Goller ,  Gerald Holweg ,  Thomas Herndl

IPC: G06K19/06 ,  G06K19/077 ,  G06K19/073 ,  G06K19/07

CPC classification number: G06K19/07758 ,  G06K19/0704 ,  G06K19/0705 ,  G06K19/0717 ,  G06K19/0723 ,  G06K19/073

Abstract: A semiconductor device includes a semiconductor substrate having an upper first main face and first and second recess areas formed in the upper first main face, a battery arranged at the first recess area and one or more of a shock sensor and an acceleration sensor arranged at the second recess area. The shock sensor or the acceleration sensor includes a movable mass, a cantilever connected to the moveable mass, a piezoelectric layer applied to the cantilever, and a wiring connected to the piezoelectric layer. The wiring has first and second terminals. The moveable mass and part of the cantilever are arranged above the second recess area, so that the shock sensor or the acceleration sensor delivers a voltage between the first and second terminals, a strength of the voltage being dependent on a strength of a shock or acceleration exerted on the semiconductor device.

公开(公告)号：US20150280288A1

公开(公告)日：2015-10-01

申请号：US14230071

申请日：2014-03-31

Applicant: Infineon Technologies AG

Inventor： Vijaye Kumar Rajaraman ,  Kamil Karlovsky ,  Thomas Neidhart ,  Karl Mayer ,  Rainer Leuschner ,  Christine Moser ,  Ravi Keshav Joshi ,  Alexander Breymesser ,  Bernhard Goller ,  Francisco Javier Santos Rodriguez ,  Peter Zorn

IPC: H01M10/42 ,  H01M2/08 ,  H01M10/04 ,  H01M2/02

CPC classification number: H01M10/4257 ,  H01M2/0202 ,  H01M2/024 ,  H01M2/0404 ,  H01M2/06 ,  H01M2/08 ,  H01M6/40 ,  H01M10/04 ,  H01M10/0436 ,  H01M10/052 ,  Y10T29/4911

Abstract: A lithium ion battery includes a first substrate having a first main surface, and a lid including an insulating material. The lid is attached to the first main surface of the first substrate, and a cavity is defined between the first substrate and the lid. The lithium ion battery further includes an electrical interconnection element in the lid, the electrical interconnection element providing an electrical connection between a first main surface and a second main surface of the lid. The lithium ion battery further includes an electrolyte in the cavity, an anode at the first substrate, the anode including a component made of a semiconductor material, and a cathode at the lid.

Abstract translation: 锂离子电池包括具有第一主表面的第一基板和包括绝缘材料的盖。 盖子附接到第一基板的第一主表面，并且在第一基板和盖子之间限定空腔。 锂离子电池还包括盖中的电互连元件，电互连元件在盖的第一主表面和第二主表面之间提供电连接。 锂离子电池还包括空腔中的电解质，第一衬底处的阳极，阳极包括由半导体材料制成的部件，以及阴极。

公开(公告)号：US12211703B2

公开(公告)日：2025-01-28

申请号：US18236434

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Alexander Breymesser ,  Bernhard Goller ,  Matthias Kuenle ,  Helmut Oefner ,  Francisco Javier Santos Rodriguez ,  Stephan Voss

IPC: H01L21/324 ,  H01L21/265 ,  H01L21/78

Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

公开(公告)号：US11712749B2

公开(公告)日：2023-08-01

申请号：US16986411

申请日：2020-08-06

Applicant: Infineon Technologies AG

Inventor： Ralf Rieske ,  Alexander Binter ,  Wolfgang Diewald ,  Bernhard Goller ,  Heimo Graf ,  Gerald Lackner ,  Jan Richter ,  Roland Rupp ,  Guenter Schagerl ,  Marko Swoboda

IPC: B23K26/0622 ,  H01L21/02 ,  B23K26/00 ,  H01L21/78

CPC classification number: B23K26/0624 ,  B23K26/0006 ,  H01L21/02378 ,  H01L21/7813

Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.