公开(公告)号：US11127693B2

公开(公告)日：2021-09-21

申请号：US16710044

申请日：2019-12-11

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Katrin Albers ,  Joerg Busch ,  Klaus Goller ,  Norbert Mais ,  Marianne Kolitsch ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00 ,  B81B7/00 ,  H01L23/58

Abstract: A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.

公开(公告)号：US11031321B2

公开(公告)日：2021-06-08

申请号：US16354392

申请日：2019-03-15

Applicant: Infineon Technologies AG

Inventor： Rainer Pelzer ,  Fortunato Lopez ,  Antonia Maglangit ,  Siti Amira Faisha Shikh Zakaria

IPC: H01L23/495 ,  H01L21/768 ,  H01L21/48 ,  H01L23/532

Abstract: A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described.

公开(公告)号：US10700019B2

公开(公告)日：2020-06-30

申请号：US16418006

申请日：2019-05-21

Applicant: Infineon Technologies AG

Inventor： Marianne Mataln ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00 ,  H01L23/58 ,  B81B7/00

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

公开(公告)号：US20180145045A1

公开(公告)日：2018-05-24

申请号：US15817810

申请日：2017-11-20

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Rainer Pelzer ,  Manfred Schneegans

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/4502 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/45099

Abstract: A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

公开(公告)号：US10304782B2

公开(公告)日：2019-05-28

申请号：US15686576

申请日：2017-08-25

Applicant: Infineon Technologies AG

Inventor： Marianne Mataln ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having defined edges, and a structured metallization on the structured interlayer and also having defined edges. Each defined edge of the structured interlayer neighbors one of the defined edges of the structured metallization and runs in the same direction as the neighboring defined edge of the structured metallization. Each defined edge of the structured interlayer extends beyond the neighboring defined edge of the structured metallization by at least 0.5 microns so that each defined edge of the structured metallization terminates before reaching the neighboring defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature.

公开(公告)号：US08884407B2

公开(公告)日：2014-11-11

申请号：US13693481

申请日：2012-12-04

Applicant: Infineon Technologies AG

Inventor： Michael Sternad ,  Rainer Pelzer

IPC: H01L23/552 ,  H01R43/02 ,  G02B19/00 ,  H01L23/498

CPC classification number: H01R43/02 ,  B23K26/22 ,  B23K2101/38 ,  G02B19/0028 ,  G02B19/0047 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/78263 ,  H01L2224/78301 ,  H01L2224/85039 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A device includes a tube extending in a longitudinal direction and a hollow channel arranged in the tube. An end part of the tube is formed such that first electromagnetic radiation paths extending in the tube and outside of the hollow channel in the longitudinal direction are focused in a first focus.

Abstract translation: 一种装置包括沿纵向延伸的管和布置在管中的中空通道。 管的端部形成为使得沿着纵向方向在管中延伸到中空通道外部的第一电磁辐射路径被聚焦在第一焦点中。

公开(公告)号：US11488921B2

公开(公告)日：2022-11-01

申请号：US17060434

申请日：2020-10-01

Applicant: Infineon Technologies AG

Inventor： Ali Roshanghias ,  Alfred Binder ,  Barbara Eichinger ,  Stefan Karner ,  Martin Mischitz ,  Rainer Pelzer

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.

公开(公告)号：US20190067209A1

公开(公告)日：2019-02-28

申请号：US15686576

申请日：2017-08-25

Applicant: Infineon Technologies AG

Inventor： Marianne Mataln ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having defined edges, and a structured metallization on the structured interlayer and also having defined edges. Each defined edge of the structured interlayer neighbors one of the defined edges of the structured metallization and runs in the same direction as the neighboring defined edge of the structured metallization. Each defined edge of the structured interlayer extends beyond the neighboring defined edge of the structured metallization by at least 0.5 microns so that each defined edge of the structured metallization terminates before reaching the neighboring defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature.

公开(公告)号：US11239188B2

公开(公告)日：2022-02-01

申请号：US15817810

申请日：2017-11-20

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Rainer Pelzer ,  Manfred Schneegans

IPC: H01L23/00

Abstract: A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

公开(公告)号：US20210098410A1

公开(公告)日：2021-04-01

申请号：US17060434

申请日：2020-10-01

Applicant: Infineon Technologies AG

Inventor： Ali Roshanghias ,  Alfred Binder ,  Barbara Eichinger ,  Stefan Karner ,  Martin Mischitz ,  Rainer Pelzer

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.