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    ENFORCING MEMORY OPERAND TYPES USING PROTECTION KEYS
    1.
    发明申请
    ENFORCING MEMORY OPERAND TYPES USING PROTECTION KEYS 有权

    公开(公告)号：US20210117343A1

    公开(公告)日：2021-04-22

    申请号：US17133734

    申请日：2020-12-24

    申请人： Intel Corporation

    发明人： Michael Lemay ,  David A. Koufaty ,  Ravi L. Sahita

    IPC分类号： G06F12/14 ,  G06F21/53 ,  G06F21/56

    摘要： Enforcing memory operand types using protection keys is generally described herein. A processor system to provide sandbox execution support for protection key rights attacks includes a processor core to execute a task associated with an untrusted application and execute the task using a designated page of a memory; and a memory management unit to designate the page of the memory to support execution of the untrusted application.

    Access control for memory protection key architecture
    6.
    发明授权
    Access control for memory protection key architecture 有权

    公开(公告)号：US09910611B2

    公开(公告)日：2018-03-06

    申请号：US14725130

    申请日：2015-05-29

    申请人： INTEL CORPORATION

    发明人： David A. Koufaty ,  Ravi L. Sahita

    IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/14 ,  G06F12/1009 ,  G06F12/08

    CPC分类号： G06F3/0622 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/145 ,  G06F12/1466 ,  G06F12/1475 ,  G06F2212/1052

    摘要： A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a protection key register comprising a plurality of fields. Each field comprising a set of bits reflecting a memory access permission for each of a plurality of memory domains. The memory management unit also includes a plurality of protection key mask registers. Each of the protection key mask registers comprising a mask having a plurality of bits, each bit reflecting an access permission to a corresponding field of the protection key register by a code page residing in a memory domain of the plurality of memory domains identified by an index of the protection key mask register. The memory management unit is, responsive to receiving a request to modify the protection key register by the code page residing in the memory domain, to select a protection key mask register among the plurality of protection key mask registers and to apply a mask comprised by selected protection key mask register indexed by an identifier of the memory domain.

    ACCESS CONTROL FOR MEMORY PROTECTION KEY ARCHITECTURE
    8.
    发明申请
    ACCESS CONTROL FOR MEMORY PROTECTION KEY ARCHITECTURE 有权
    存储器保护关键体系结构的访问控制

    公开(公告)号：US20160350019A1

    公开(公告)日：2016-12-01

    申请号：US14725130

    申请日：2015-05-29

    申请人： INTEL CORPORATION

    发明人： David A. Koufaty ,  Ravi L. Sahita

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0622 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/145 ,  G06F12/1466 ,  G06F12/1475 ,  G06F2212/1052

    摘要： A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a protection key register comprising a plurality of fields. Each field comprising a set of bits reflecting a memory access permission for each of a plurality of memory domains. The memory management unit also includes a plurality of protection key mask registers. Each of the protection key mask registers comprising a mask having a plurality of bits, each bit reflecting an access permission to a corresponding field of the protection key register by a code page residing in a memory domain of the plurality of memory domains identified by an index of the protection key mask register. The memory management unit is, responsive to receiving a request to modify the protection key register by the code page residing in the memory domain, to select a protection key mask register among the plurality of protection key mask registers and to apply a mask comprised by selected protection key mask register indexed by an identifier of the memory domain.

    摘要翻译： 处理系统包括执行任务的处理核心和耦合到核心的存储器管理单元。 存储器管理单元包括包括多个场的保护密钥寄存器。 每个字段包括反映多个存储器域中的每一个的存储器访问许可的一组位。 存储器管理单元还包括多个保护密钥掩码寄存器。 每个保护密钥掩码寄存器包括具有多个位的掩码，每个位反映由驻留在由索引识别的多个存储器域的存储器域中的代码页对保护密钥寄存器的相应字段的访问许可 的保护键盘掩码寄存器。 存储器管理单元响应于通过驻留在存储器域中的代码页接收到修改保护密钥寄存器的请求，以选择多个保护密钥掩码寄存器中的保护密钥掩码寄存器，并且应用由选择的掩码包括的掩码 保护密钥掩码寄存器由存储器域的标识符索引。

    Remote atomic operations in multi-socket systems
    9.
    发明授权
    Remote atomic operations in multi-socket systems 有权

    公开(公告)号：US11537520B2

    公开(公告)日：2022-12-27

    申请号：US17494651

    申请日：2021-10-05

    申请人： Intel Corporation

    发明人： Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  Christopher J. Hughes ,  Jonas Svennebring ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  David A. Koufaty

    IPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0817 ,  G06F12/0831

    摘要： Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.