-
公开(公告)号:US20220183177A1
公开(公告)日:2022-06-09
申请号:US17677785
申请日:2022-02-22
Applicant: Intel Corporation
Inventor: Zhichao ZHANG , Gregorio R. MURTAGIAN , Kuang C. LIU , Kemal AYGUN
Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
-
公开(公告)号:US20180192519A1
公开(公告)日:2018-07-05
申请号:US15855808
申请日:2017-12-27
Applicant: INTEL CORPORATION
Inventor: Fay HUA , Hong XIE , Gregorio R. MURTAGIAN , Amit ABRAHAM , Alan C. MCALLISTER , Ting ZHONG
CPC classification number: H05K1/181 , H01L23/49811 , H01L23/49816 , H01L2224/00 , H01R12/52 , H01R33/7607 , H05K3/3421 , H05K3/4007 , H05K2201/10719
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.
-
公开(公告)号:US20210307153A1
公开(公告)日:2021-09-30
申请号:US16828447
申请日:2020-03-24
Applicant: Intel Corporation
Inventor: Feroz MOHAMMAD , Ralph V. MIELE , Thomas BOYD , Steven A. KLEIN , Gregorio R. MURTAGIAN , Eric W. BUDDRIUS , Daniel NEUMANN , Rolf LAIDO
Abstract: Embodiments disclosed herein include assemblies. In an embodiment, an assembly comprises a socket and a bolster plate on a board, where the bolster plate has load studs and an opening that surrounds the socket; a shim having first and second ends; and a carrier on the bolster plate, where the carrier has an opening and cutouts. The shim may have an opening through the first end as the second end is affixed to the carrier. The opening of the shim entirely over one cutout from a corner region of the carrier. In an embodiment, the assembly comprises an electronic package in the opening of the carrier, where the electronic package is affixed to the carrier, and a heatsink over the electronic package and carrier, where the first end is directly coupled to a surface of the heatsink and a surface of one load stud of the bolster plate.
-
公开(公告)号:US20180331043A1
公开(公告)日:2018-11-15
申请号:US15774257
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Yu Amos ZHANG , Zhiguo QIAN , Kemal AYGUN , Yidnekachew S. MEKONNEN , Gregorio R. MURTAGIAN , Sanka GANESAN , Eduard ROYTMAN , Jeff C. MORRISS
IPC: H01L23/538 , H01L23/66 , H01L23/552
CPC classification number: H01L23/5384 , H01L23/48 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L23/552 , H01L23/66 , H01L24/00 , H01L25/0655 , H01L2224/131 , H01L2224/16227 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/15192 , H01L2924/15311 , H01L2924/3025 , H01L2924/014 , H01L2924/00014
Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.
-
公开(公告)号:US20250149414A1
公开(公告)日:2025-05-08
申请号:US18504352
申请日:2023-11-08
Applicant: Intel Corporation
Inventor: Ziyin LIN , Karumbu MEYYAPPAN , Gregorio R. MURTAGIAN , Dingying David XU
IPC: H01L23/498 , H01L23/00
Abstract: Embodiments disclosed herein include an interconnect structure. In an embodiment, the interconnect structure is an apparatus that comprises a substrate with a well through a thickness of the substrate. In an embodiment, the substrate comprises a polymer foam. In an embodiment, a liquid metal is in the opening, and the liquid metal comprises voids.
-
公开(公告)号:US20240388018A1
公开(公告)日:2024-11-21
申请号:US18199269
申请日:2023-05-18
Applicant: Intel Corporation
Inventor: Karumbu MEYYAPPAN , Gregorio R. MURTAGIAN , Ziyin LIN
IPC: H01R12/52 , H01L23/498 , H01R3/08 , H05K1/18 , H05K3/32
Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a first surface and a second surface opposite from the first surface. In an embodiment, pads are on the first surface of the package substrate, where the pads have a first width. In an embodiment, a layer is on the first surface of the package substrate, where the layer comprises wells through the layer, and where the wells have a second width that is wider than the first width. In an embodiment, a liquid metal is in the wells and in contact with the pads.
-
公开(公告)号:US20220308294A1
公开(公告)日:2022-09-29
申请号:US17214035
申请日:2021-03-26
Applicant: Intel Corporation
Inventor: Wesley MORGAN , Srikant NEKKANTY , Todd R. COONS , Gregorio R. MURTAGIAN , Xiaoqian LI , Nitin DESHPANDE , Divya PRATAP
IPC: G02B6/42
Abstract: Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.
-
公开(公告)号:US20160338199A1
公开(公告)日:2016-11-17
申请号:US14780501
申请日:2014-12-20
Applicant: Intel Corporation
Inventor: Fay HUA , Hong XIE , Gregorio R. MURTAGIAN , Amit ABRAHAM , Alan C. MCALLISTER , Ting ZHONG
CPC classification number: H05K1/181 , H01L23/49811 , H01L23/49816 , H01L2224/00 , H01R12/52 , H01R33/7607 , H05K3/3421 , H05K3/4007 , H05K2201/10719
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例涉及提供用于插座组件中的电连接的焊接触点的技术和配置。 在一个实施例中,焊料接触可以设置在管芯封装的底表面上,使得焊料接触件导电地耦合到管芯封装的电触头。 焊接触点可以被设置成耦合到插座组件的引脚,以提供模具封装的电触点和插座组件的引脚的导电耦合。 可以选择焊料足够软以提供更好的导电性。 引脚还可以被配置为穿透焊接触点以提供更好的导电性。 可以描述和/或要求保护其他实施例。
-
-
-
-
-
-
-