公开(公告)号：US20190259622A1

公开(公告)日：2019-08-22

申请号：US16399703

申请日：2019-04-30

Applicant: INTEL CORPORATION

Inventor： Sasha N. OSTER ,  Fay HUA ,  Telesphor KAMGAING ,  Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Johanna M. SWAN

IPC: H01L21/285 ,  B82Y40/00 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/033 ,  H01L25/16 ,  H05K1/16 ,  H05K3/28 ,  H01L23/66

Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.

公开(公告)号：US20180047689A1

公开(公告)日：2018-02-15

申请号：US15555434

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Fay HUA

IPC: H01L23/00

CPC classification number: H01L24/13 ,  B23K35/00 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/08503 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/206 ,  H01L2924/3512 ,  H01L2924/3651 ,  H01L2924/0103 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01013

Abstract: Embodiments of the invention include a semiconductor device and methods of forming the semiconductor device. In an embodiment the semiconductor device comprises a semiconductor die with one or more die contacts. Embodiments include a reflown solder bump on one or more of the die contacts. In an embodiment, an intermetallic compound (IMC) barrier layer is formed at the interface between the solder bump and the die contact. In an embodiment, the IMC barrier layer is a CuZn IMC and/or a Cu5Zn8 IMC.

公开(公告)号：US20210193613A1

公开(公告)日：2021-06-24

申请号：US16080989

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Fay HUA ,  Christopher M. PELTO ,  Valluri R. RAO ,  Mark T. BOHR ,  Johanna M. SWAN

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L21/768 ,  H01L25/00 ,  H01L21/02

Abstract: Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.

公开(公告)号：US20180286687A1

公开(公告)日：2018-10-04

申请号：US15476842

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Sasha N. OSTER ,  Fay HUA ,  Telesphor KAMGAING ,  Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Johanna M. SWAN

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/033 ,  G03F7/16 ,  B82Y40/00

CPC classification number: H01L21/28562 ,  B82Y40/00 ,  H01L21/033 ,  H01L21/76822 ,  H01L21/76834

Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.

公开(公告)号：US20180192519A1

公开(公告)日：2018-07-05

申请号：US15855808

申请日：2017-12-27

Applicant: INTEL CORPORATION

Inventor： Fay HUA ,  Hong XIE ,  Gregorio R. MURTAGIAN ,  Amit ABRAHAM ,  Alan C. MCALLISTER ,  Ting ZHONG

IPC: H05K1/18 ,  H01R12/52 ,  H05K3/34 ,  H01L23/498 ,  H05K3/40 ,  H01R33/76

CPC classification number: H05K1/181 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/00 ,  H01R12/52 ,  H01R33/7607 ,  H05K3/3421 ,  H05K3/4007 ,  H05K2201/10719

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.

公开(公告)号：US20180098428A1

公开(公告)日：2018-04-05

申请号：US15283352

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Fay HUA ,  Brandon M. RAWLINGS ,  Georgios C. DOGIAMIS ,  Telesphor KAMGAING

IPC: H05K1/16 ,  H01L23/498 ,  H01L21/48 ,  H05K3/42 ,  H05K3/00 ,  H01L25/16 ,  H05K1/11

Abstract: Embodiments are generally directed to non-planar on-package via capacitor. An embodiment of an embedded capacitor includes a first plate that is formed in a package via; a dielectric layer that is applied on the first plate; and a second plate that is formed in a cavity in the dielectric layer, wherein the first plate and the second plate are non-planar plates.

公开(公告)号：US20170154790A1

公开(公告)日：2017-06-01

申请号：US14954359

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Fay HUA ,  Aranzazu MAESTRE CARO

IPC: H01L21/48 ,  H01L23/498

CPC classification number: C23C18/2006 ,  C23C18/165 ,  H01L21/481 ,  H01L21/4846

Abstract: A method including activating an area of a polymer layer on a substrate with electromagnetic radiation; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with the self-assembled monolayer; and reacting the self-assembled monolayer with a conductive material. A method including activating an area of a polymer dielectric layer on a substrate with electromagnetic radiation, the area selected for an electrically conductive line; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with a catalyst; and electroless plating a conductive material on the self-assembled monolayer.

公开(公告)号：US20190326258A1

公开(公告)日：2019-10-24

申请号：US16399726

申请日：2019-04-30

Applicant: INTEL CORPORATION

Inventor： Fay HUA ,  Telesphor KAMGAING ,  Johanna M. SWAN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/64 ,  H01L21/02 ,  H01L23/29 ,  H01L23/48 ,  H01L23/31 ,  H01L25/00

Abstract: Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising active elements and a backside opposite the front side. The device includes a dielectric layer on the backside, and a passive component on the dielectric layer on the backside. In certain embodiments, the passive device is formed on a self-assembled monolayer (SAM). Other embodiments are described and claimed.

公开(公告)号：US20180305818A1

公开(公告)日：2018-10-25

申请号：US15769699

申请日：2015-08-08

Applicant: Intel Corporation

Inventor： Fay HUA ,  Aranzazu MAESTRE CARO

IPC: C23C18/20 ,  H01L21/48 ,  H01L23/498 ,  C23C18/16

Abstract: A method including activating an area of a polymer layer on a substrate with electromagnetic radiation; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with the self-assembled monolayer; and reacting the self-assembled monolayer with a conductive material. A method including activating an area of a polymer dielectric layer on a substrate with electro-magnetic radiation, the area selected for an electrically conductive line; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with a catalyst; and electroless plating a conductive material on the self-assembled monolayer.

公开(公告)号：US20180286834A1

公开(公告)日：2018-10-04

申请号：US15476872

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Fay HUA ,  Telesphor KAMGAING ,  Johanna M. SWAN

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L25/0657 ,  H01L21/022 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/64 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05164 ,  H01L2224/06181 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/1903 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/00014

Abstract: Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising active elements and a backside opposite the front side. The device includes a dielectric layer on the backside, and a passive component on the dielectric layer on the backside. In certain embodiments, the passive device is formed on a self-assembled monolayer (SAM). Other embodiments are described and claimed.