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1.发明申请公开(公告)号：US20240429301A1
公开(公告)日：2024-12-26
申请号：US18341467
申请日：2023-06-26
Applicant: Intel Corporation
Inventor： Rachel A. Steinhardt , Dmitri Evgenievich Nikonov , Kevin P. O'Brien , John J. Plombon , Tristan A. Tronic , Ian Alexander Young , Matthew V. Metz , Marko Radosavljevic , Carly Rogan , Brandon Holybee , Raseong Kim , Punyashloka Debashis , Dominique A. Adams , I-Cheng Tung , Arnab Sen Gupta , Gauri Auluck , Scott B. Clendenning , Pratyush P. Buragohain
IPC: H01L29/423 , H01L29/06 , H01L29/66 , H01L29/786
Abstract: A transistor device may be formed with a doped perovskite material as a channel region. The doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.
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公开(公告)号：US12009018B2
公开(公告)日：2024-06-11
申请号：US17839345
申请日：2022-06-13
Applicant: Intel Corporation
Inventor： Chia-Ching Lin , Sasikanth Manipatruni , Tanay Gosavi , Dmitri Nikonov , Benjamin Buford , Kaan Oguz , John J. Plombon , Ian A. Young
CPC classification number: G11C11/161 , H10N50/80 , H10N50/85
Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.
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公开(公告)号：US20240105822A1
公开(公告)日：2024-03-28
申请号：US17953648
申请日：2022-09-27
Applicant: Intel Corporation
Inventor： Kevin P. O'Brien , Brandon Holybee , Carly Rogan , Dmitri Evgenievich Nikonov , Punyashloka Debashis , Rachel A. Steinhardt , Tristan A. Tronic , Ian Alexander Young , Marko Radosavljevic , John J. Plombon
IPC: H01L29/775 , H01L29/06 , H01L29/24 , H01L29/423 , H01L29/49 , H01L29/66
CPC classification number: H01L29/775 , H01L29/0673 , H01L29/24 , H01L29/42392 , H01L29/4908 , H01L29/66969
Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.
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公开(公告)号：US20230200079A1
公开(公告)日：2023-06-22
申请号：US17555207
申请日：2021-12-17
Applicant: Intel Corporation
Inventor： Chia-Ching Lin , Tanay A. Gosavi , Uygar E. Avci , Sou-Chi Chang , Hai Li , Dmitri Evgenievich Nikonov , Kaan Oguz , Ashish Verma Penumatcha , John J. Plombon , Ian Alexander Young
IPC: H01L27/11514 , H01L49/02 , H01L29/51
CPC classification number: H01L27/11514 , H01L28/65 , H01L29/516
Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.
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公开(公告)号：US20220310147A1
公开(公告)日：2022-09-29
申请号：US17839345
申请日：2022-06-13
Applicant: Intel Corporation
Inventor： Chia-Ching Lin , Sasikanth Manipatruni , Tanay Gosavi , Dmitri Nikonov , Benjamin Buford , Kaan Oguz , John J. Plombon , Ian A. Young
Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.
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Patent Agency Ranking
公开(公告)号：US20220123206A1
公开(公告)日：2022-04-21
申请号：US17565106
申请日：2021-12-29
Applicant: Intel Corporation
Inventor： Chia-Ching Lin , Sasikanth Manipatruni , Tanay Gosavi , Dmitri Nikonov , Benjamin Buford , Kaan Oguz , John J. Plombon , Ian A. Young
Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.
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公开(公告)号：US20250006841A1
公开(公告)日：2025-01-02
申请号：US18345127
申请日：2023-06-30
Applicant: Intel Corporation
Inventor： Arnab Sen Gupta , Dmitri Evgenievich Nikonov , John J. Plombon , Rachel A. Steinhardt , Punyashloka Debashis , Kevin P. O'Brien , Matthew V. Metz , Scott B. Clendenning , Brandon Holybee , Marko Radosavljevic , Ian Alexander Young , I-Cheng Tung , Sudarat Lee , Raseong Kim , Pratyush P. Buragohain
IPC: H01L29/78 , H01L29/06 , H01L29/221 , H01L29/423 , H01L29/775 , H01L29/786
Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.
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公开(公告)号：US20250006839A1
公开(公告)日：2025-01-02
申请号：US18343203
申请日：2023-06-28
Applicant: Intel Corporation
Inventor： Kevin P. O'Brien , Dmitri Evgenievich Nikonov , Rachel A. Steinhardt , Pratyush P. Buragohain , John J. Plombon , Hai Li , Gauri Auluck , I-Cheng Tung , Tristan A. Tronic , Dominique A. Adams , Punyashloka Debashis , Raseong Kim , Carly Rogan , Arnab Sen Gupta , Brandon Holybee , Marko Radosavljevic , Uygar E. Avci , Ian Alexander Young , Matthew V. Metz
Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.
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公开(公告)号：US11696514B2
公开(公告)日：2023-07-04
申请号：US17565106
申请日：2021-12-29
Applicant: Intel Corporation
Inventor： Chia-Ching Lin , Sasikanth Manipatruni , Tanay Gosavi , Dmitri Nikonov , Benjamin Buford , Kaan Oguz , John J. Plombon , Ian A. Young
Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.
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公开(公告)号：US11245068B2
公开(公告)日：2022-02-08
申请号：US16009035
申请日：2018-06-14
Applicant: Intel Corporation
Inventor： Chia-Ching Lin , Sasikanth Manipatruni , Tanay Gosavi , Dmitri Nikonov , Benjamin Buford , Kaan Oguz , John J. Plombon , Ian A. Young
Abstract: An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO3, (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, SmBiFeO3, Cr2O3, etc.) material and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.
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