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    Self-Aligned Gate Edge and Local Interconnect and Method to Fabricate Same
    1.
    发明申请
    Self-Aligned Gate Edge and Local Interconnect and Method to Fabricate Same 审中-公开
    自对准边缘和本地互连及其制造方法

    公开(公告)号：US20160233298A1

    公开(公告)日：2016-08-11

    申请号：US15024750

    申请日：2013-12-19

    Applicant: INTEL CORPORATION

    Inventor： Milton C. WEBB ,  Mark BOHR ,  Tahir GHANI ,  Szuya S. LIAO

    IPC: H01L29/06 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/417

    CPC classification number: H01L29/0649 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

    Abstract translation: 描述了自对准栅极边缘和局部互连结构以及制造自对准栅极边缘和局部互连结构的方法。 在一个示例中，半导体结构包括设置在基板上方并且具有沿第一方向的长度的半导体鳍片。 栅极结构设置在半导体鳍上方，栅极结构具有与第一方向正交的第二端相对于第二端的第一端。 一对栅极边缘隔离结构以半导体鳍为中心。 一对栅极边缘隔离结构中的第一个直接邻近栅极结构的第一端设置，并且该对栅极边缘隔离结构中的第二个直接邻近栅极结构的第二端设置。

    DEVICE, METHOD AND SYSTEM FOR PROVIDING A STACKED ARRANGEMENT OF INTEGRATED CIRCUIT DIES
    2.
    发明申请
    DEVICE, METHOD AND SYSTEM FOR PROVIDING A STACKED ARRANGEMENT OF INTEGRATED CIRCUIT DIES 有权

    公开(公告)号：US20210074695A1

    公开(公告)日：2021-03-11

    申请号：US16646460

    申请日：2017-12-28

    Applicant: Intel Corporation

    Inventor： Wilfred GOMES ,  Mark BOHR ,  Glenn J. HINTON ,  Rajesh KUMAR

    IPC: H01L25/18 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00

    Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

    SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME
    3.
    发明申请
    SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME 审中-公开

    公开(公告)号：US20190326391A1

    公开(公告)日：2019-10-24

    申请号：US16398995

    申请日：2019-04-30

    Applicant: Intel Corporation

    Inventor： Milton Clair WEBB ,  Mark BOHR ,  Tahir GHANI ,  Szuya S. LIAO

    IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/78 ,  H01L23/535 ,  H01L29/417

    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

    COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT
    8.
    发明申请
    COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT 有权

    公开(公告)号：US20220115505A1

    公开(公告)日：2022-04-14

    申请号：US17558425

    申请日：2021-12-21

    Applicant: Intel Corporation

    Inventor： Kelin J. KUHN ,  Kaizad MISTRY ,  Mark BOHR ,  Chris AUTH

    IPC: H01L29/417 ,  H01L21/768 ,  H01L23/485 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

    DESIGNS AND METHODS FOR CONDUCTIVE BUMPS
    9.
    发明申请
    DESIGNS AND METHODS FOR CONDUCTIVE BUMPS 有权

    公开(公告)号：US20220059484A1

    公开(公告)日：2022-02-24

    申请号：US17519468

    申请日：2021-11-04

    Applicant: Intel Corporation

    Inventor： Valery M. DUBIN ,  Sridhar BALAKRISHNAN ,  Mark BOHR

    IPC: H01L23/00 ,  H01L21/288 ,  H01L21/48

    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

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