公开(公告)号：US20140097434A1

公开(公告)日：2014-04-10

申请号：US13644918

申请日：2012-10-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L29/775 ,  G06F17/50 ,  H01L21/336

CPC classification number: H01L29/93 ,  H01L27/0688 ,  H01L27/0808

Abstract: Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.

Abstract translation: 变容二极管的器件结构，设计结构和制造方法。 器件结构包括形成在电介质层上的第一电极和形成在第一电极上的半导体本体。 半导体本体由非晶态或多晶态的含硅半导体材料构成。 器件结构还包括形成在半导体主体上的电极绝缘体和形成在电极绝缘体上的第二电极。

公开(公告)号：US09087808B2

公开(公告)日：2015-07-21

申请号：US14451836

申请日：2014-08-05

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Junjun Li ,  Xuefeng Liu ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L21/36 ,  H01L21/84 ,  H01L27/12 ,  B81C1/00

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B2207/094 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/84 ,  H01L27/1203

Abstract: A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

公开(公告)号：US20150014771A1

公开(公告)日：2015-01-15

申请号：US13939353

申请日：2013-07-11

Applicant: International Business Machines Corporation

Inventor： David G. Brochu, JR. ,  John J. Ellis-Monaghan ,  Michael J. Hauser ,  Jeffrey B. Johnson ,  Xuefeng Liu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66681 ,  H01L29/732 ,  H01L29/7816

Abstract: A semiconductor device comprising dual L-shaped drift regions in a lateral diffused metal oxide semiconductor (LDMOS) and a method of making the same. The LDMOS in the semiconductor device comprises a trench isolation region or a deep trench encapsulated by a liner, a first L-shaped drift region, and a second L-shaped drift region. The LDMOS comprising the dual L-shape drift regions is integrated with silicon-germanium (SiGe) technology. The LDMOS comprising the dual L-shape drift regions furnishes a much higher voltage drop in a lateral direction within a much shorter distance from a drain region than the traditional LDMOS does.

Abstract translation: 在横向扩散金属氧化物半导体（LDMOS）中包括双L型漂移区域的半导体器件及其制造方法。 半导体器件中的LDMOS包括由衬垫封装的沟槽隔离区域或深沟槽，第一L形漂移区域和第二L形漂移区域。 包括双L形漂移区的LDMOS与硅 - 锗（SiGe）技术集成。 包括双L形漂移区域的LDMOS在距离漏极区域比传统的LDMOS短得多的距离内在横向上提供高得多的电压降。

公开(公告)号：US08809155B2

公开(公告)日：2014-08-19

申请号：US13644918

申请日：2012-10-04

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L21/336

CPC classification number: H01L29/93 ,  H01L27/0688 ,  H01L27/0808

Abstract: Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.

Abstract translation: 变容二极管的器件结构，设计结构和制造方法。 器件结构包括形成在电介质层上的第一电极和形成在第一电极上的半导体本体。 半导体本体由非晶态或多晶态的含硅半导体材料构成。 器件结构还包括形成在半导体主体上的电极绝缘体和形成在电极绝缘体上的第二电极。

公开(公告)号：US09059281B2

公开(公告)日：2015-06-16

申请号：US13939353

申请日：2013-07-11

Applicant: International Business Machines Corporation

Inventor： David G. Brochu, Jr. ,  John J. Ellis-Monaghan ,  Michael J. Hauser ,  Jeffrey B. Johnson ,  Xuefeng Liu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/732 ,  H01L29/08 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L29/7833 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66681 ,  H01L29/732 ,  H01L29/7816

Abstract: A semiconductor device comprising dual L-shaped drift regions in a lateral diffused metal oxide semiconductor (LDMOS) and a method of making the same. The LDMOS in the semiconductor device comprises a trench isolation region or a deep trench encapsulated by a liner, a first L-shaped drift region, and a second L-shaped drift region. The LDMOS comprising the dual L-shape drift regions is integrated with silicon-germanium (SiGe) technology. The LDMOS comprising the dual L-shape drift regions furnishes a much higher voltage drop in a lateral direction within a much shorter distance from a drain region than the traditional LDMOS does.

Abstract translation: 在横向扩散金属氧化物半导体（LDMOS）中包括双L型漂移区域的半导体器件及其制造方法。 半导体器件中的LDMOS包括由衬垫封装的沟槽隔离区域或深沟槽，第一L形漂移区域和第二L形漂移区域。 包括双L形漂移区的LDMOS与硅 - 锗（SiGe）技术集成。 包括双L形漂移区域的LDMOS在距离漏极区域比传统的LDMOS短得多的距离内在横向上提供高得多的电压降。

公开(公告)号：US08951893B2

公开(公告)日：2015-02-10

申请号：US13733243

申请日：2013-01-03

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Junjun Li ,  Xuefeng Liu ,  Anthony K. Stamper

IPC: H01L27/04 ,  H01L21/36 ,  H01L21/84 ,  H01L27/12

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B2207/094 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/84 ,  H01L27/1203

Abstract: A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

Abstract translation: 描述了半导体制造，其中在BEOL工艺中同时制造MOS器件和MEMS器件。 沉积并蚀刻硅层以形成用于MOS器件的硅膜和用于MEMS器件的下硅牺牲膜。 导电层沉积在硅层顶部并被蚀刻以形成金属栅极和第一上电极。 介电层沉积在导电层顶上，并且通孔形成在电介质层中。 另一个导电层沉积在电介质层顶上并被蚀刻以形成用于MOS器件的第二上电极和三个金属电极。 另一硅层沉积在另一导电层的顶上，并被蚀刻以形成用于MEMS器件的上硅牺牲膜。 然后通过排气孔去除上部和下部硅牺牲膜。

公开(公告)号：US08933540B2

公开(公告)日：2015-01-13

申请号：US13780033

申请日：2013-02-28

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Michael J. Hauser ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/34 ,  H01L25/00

CPC classification number: H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589

Abstract: A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion.

Abstract translation: 提供三维集成电路（3D-IC）结构，其制造方法及其设计结构。 3D-IC结构包括具有介电层的两个芯片，通过衬底通孔（TSV）和形成在电介质层上的焊盘。 电介质层形成在每个芯片的底表面上。 垫片电连接到相应的TSV。 芯片垂直相邻配置。 第二芯片的底表面面向第一芯片的底表面。 第一芯片的焊盘通过多个导电凸块电连接到第二芯片的焊盘。 3D-IC结构还包括垂直设置在第一芯片和第二芯片之间并横向设置在相应的导电凸块之间的热通孔结构。 热通孔结构具有上部和下部。

公开(公告)号：US20140339607A1

公开(公告)日：2014-11-20

申请号：US14451836

申请日：2014-08-05

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Junjun Li ,  Xuefeng Liu ,  Anthony K. Stamper

IPC: B81C1/00

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B2207/094 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  H01L21/84 ,  H01L27/1203

Abstract: A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.

公开(公告)号：US09304335B2

公开(公告)日：2016-04-05

申请号：US14332886

申请日：2014-07-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  William M. Green ,  Michael J. Hauser ,  Edward W. Kiewra ,  Xuefeng Liu ,  Steven M. Shank

IPC: H01L21/782 ,  H01L27/14 ,  H01L29/78 ,  G02F1/025 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/40 ,  H01L29/06 ,  H01L29/49 ,  H01L27/088 ,  H01L21/306 ,  H01L29/66 ,  H01L27/06 ,  G02B6/136 ,  G02B6/12

CPC classification number: G02F1/025 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12142 ,  G02B2006/12176 ,  H01L21/30604 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/78624

Abstract: A device includes a laterally diffused metal-oxide-semiconductor (LDMOS) device integrated with an optical modulator. An optical waveguide of the optical modulator includes a silicon-containing structure in a drift region of the LDMOS device.

Abstract translation: 一种器件包括与光学调制器集成的横向扩散的金属氧化物半导体（LDMOS）器件。 光调制器的光波导包括在LDMOS器件的漂移区域中的含硅结构。

公开(公告)号：US20140239457A1

公开(公告)日：2014-08-28

申请号：US13780033

申请日：2013-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Michael J. Hauser ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/34 ,  H01L25/00

CPC classification number: H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589

Abstract: A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion.

Abstract translation: 提供三维集成电路（3D-IC）结构，其制造方法及其设计结构。 3D-IC结构包括具有介电层的两个芯片，通过衬底通孔（TSV）和形成在电介质层上的焊盘。 电介质层形成在每个芯片的底表面上。 垫片电连接到相应的TSV。 芯片垂直相邻配置。 第二芯片的底表面面向第一芯片的底表面。 第一芯片的焊盘通过多个导电凸块电连接到第二芯片的焊盘。 3D-IC结构还包括垂直设置在第一芯片和第二芯片之间并横向设置在相应的导电凸块之间的热通孔结构。 热通孔结构具有上部和下部。