公开(公告)号：US20020111010A1

公开(公告)日：2002-08-15

申请号：US09781121

申请日：2001-02-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

IPC: H01L021/44

CPC classification number: H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Abstract translation: 描述了用于形成适用于引线键合和焊料凸块倒装芯片连接（例如受控崩溃芯片连接（C4））的公共输入 - 输出（I / O）站点的过程。 本发明特别适用于使用铜作为互连材料的半导体芯片，其中用于制造这种芯片的软电介质容易受到结合力的损害。 本发明通过在衬垫的顶表面上提供具有贵金属的部位同时提供扩散阻挡层来保持金属互连的高导电性来降低损坏的风险。 通过提供一种在衬底中形成的特征中选择性地沉积金属层的方法来减少在衬底内形成I / O部位的工艺步骤。 由于本发明的I / O站点可以用于引线键合或焊料凸块连接，这为芯片互连选项提供了增加的灵活性，同时也降低了工艺成本。

公开(公告)号：US20040087046A1

公开(公告)日：2004-05-06

申请号：US10688418

申请日：2003-10-17

Applicant: International Business Machines Corporation.

Inventor： Madhav Datta ,  Peter A. Gruber ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  George F. Walker

IPC: H01L021/66

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K1/20 ,  B23K2101/36 ,  G01R31/2886 ,  H01L22/00 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1148 ,  H01L2224/1184 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H01L2924/00014

Abstract: A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than null of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.

Abstract translation: 公开了一种在平坦焊料凸块上测试集成电路芯片的方法以及配备有平坦焊料凸块的IC芯片。 在该方法中，首先提供具有多个接合焊盘和多个平坦焊料凸块的IC芯片，其中每个焊料凸块在多个焊盘上具有小于其直径的1/2的高度。 因此，探针线可以容易地用于接触焊料凸块上的增加的目标区域，以建立与测试电路的电连接。 探针可以容易地进行，凸块的所有Z高度基本相等。 焊料凸块的高度可以通过平面化处理来适当地控制，其中软焊料凸块被平面表面压缩，或者通过用于形成焊料凸块的MSS或电镀工艺在原位模具中形成焊料凸块 呈短圆柱形。 当使用MSS方法种植凸块时，焊料凸块以大致平坦的半球形转移到晶片表面上。

公开(公告)号：US20030089962A1

公开(公告)日：2003-05-15

申请号：US09992344

申请日：2001-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC: H01L021/82 ,  H01L029/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract translation: 用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。 保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。 界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。 熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。 保险丝元件是电镀，无电镀，或是超薄保险丝。