公开(公告)号：US20040113278A1

公开(公告)日：2004-06-17

申请号：US10319032

申请日：2002-12-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L023/48

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

公开(公告)号：US20030213998A1

公开(公告)日：2003-11-20

申请号：US10146072

申请日：2002-05-16

申请人： International Business Machines Corporation

发明人： Louis Lu-Chen Hsu ,  Chandrasekhar Narayan ,  Carl J. Radens

IPC分类号： H01L023/62

CPC分类号： H01L23/5254 ,  H01L23/5252 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A non-ablative structure and method for forming a variable resistor includes providing a programmable resistive element including two or more different conductive materials, and changing a resistance of the programmable resistive element to a finite value by heating the programmable element by either providing a current flow through the programmable element, or directing a laser beam onto the programmable element. The conductive materials are interdiffused to form an alloy of the conductive materials. A resistance value of the variable resistor is determined, at least in part, by the degree to which the conductive materials are alloyed or interdiffused. The method and structure of the variable resistor prevents ablative damage to adjoining circuit structure, allowing tighter pitch, and has application to digital programmable elements, and to resistance trimming for impedance matching in RF integrated circuits.

摘要翻译： 用于形成可变电阻器的非烧蚀结构和方法包括提供包括两个或多个不同导电材料的可编程电阻元件，并且通过加热可编程元件来提供可编程电阻元件的电流来改变可编程电阻元件的有限值， 通过可编程元件，或将激光束引导到可编程元件上。 导电材料相互扩散以形成导电材料的合金。 可变电阻器的电阻值至少部分地由导电材料合金化或相互扩散的程度决定。 可变电阻器的方法和结构防止邻接电路结构的烧蚀损坏，使得更紧密的间距，并且应用于数字可编程元件，以及用于RF集成电路中的阻抗匹配的电阻调整。

公开(公告)号：US20030111733A1

公开(公告)日：2003-06-19

申请号：US10026103

申请日：2001-12-19

申请人： International Business Machines Corporation

发明人： H. Bernhard Pogge ,  Roy Yu ,  Chandrika Prasad ,  Chandrasekhar Narayan

IPC分类号： H01L023/52 ,  H01L023/48 ,  H01L029/40 ,  H01L027/108 ,  H01L029/04 ,  H01L029/76 ,  H01L029/80 ,  H01L029/94 ,  H01L031/036 ,  H01L031/112 ,  H01L031/119 ,  H01L021/4763

CPC分类号： H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

摘要翻译： 描述了在芯片级或晶片级的半导体器件集成的过程，其中通过衬底形成垂直连接。 金属化特征形成在基板的顶表面中，并且处理板附接到基板。 然后将衬底在其底表面处变薄以暴露特征的底部，以形成导电通孔。 衬底可以包括具有在其中制造的器件（例如DRAM）的芯片。 因此，该过程允许与第二芯片（例如，PE芯片）的垂直集成。 板可以是使用垂直螺柱/通孔互连连接到基板的晶片。 衬底和板可以各自具有在其中制造的器件，使得该工艺提供器件的垂直晶片级集成。

公开(公告)号：US20040113279A1

公开(公告)日：2004-06-17

申请号：US10319967

申请日：2002-12-16

申请人： International Business Machines Corporation

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P.E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L023/48 ,  H01L023/52 ,  H01L021/4763

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US20030089962A1

公开(公告)日：2003-05-15

申请号：US09992344

申请日：2001-11-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L021/82 ,  H01L029/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

摘要翻译： 用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。 保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。 界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。 熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。 保险丝元件是电镀，无电镀，或是超薄保险丝。