公开(公告)号：US20160035621A1

公开(公告)日：2016-02-04

申请号：US14883162

申请日：2015-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen CHEN ,  Jeffrey P. GAMBINO ,  Zhong-Xiang HE ,  Trevor A. THOMPSON ,  Eric J. WHITE

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/288 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

公开(公告)号：US20150332925A1

公开(公告)日：2015-11-19

申请号：US14281166

申请日：2014-05-19

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L21/288 ,  H01L23/532

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20150021793A1

公开(公告)日：2015-01-22

申请号：US14511259

申请日：2014-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. DAUBENSPECK ,  Jeffrey P. GAMBINO ,  Zhong-Xiang HE ,  Christopher D. MUZZY ,  Wolfgang SAUTER ,  Timothy D. SULLIVAN

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L24/05 ,  H01B3/306 ,  H01B3/307 ,  H01L21/02118 ,  H01L21/76877 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/48

Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

Abstract translation: 公开了使用有机绝缘材料的引线键合半导体结构和制造方法。 该方法包括在有机绝缘体层中形成金属布线层。 该方法还包括在有机绝缘体层上形成保护层。 该方法还包括在金属布线层上的有机绝缘体层中形成通孔。 该方法还包括在通孔中和保护层上沉积金属层。 该方法还包括用对有机绝缘体层有害的蚀刻化学物图案化金属层。

公开(公告)号：US20150364416A1

公开(公告)日：2015-12-17

申请号：US14832019

申请日：2015-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20150364368A1

公开(公告)日：2015-12-17

申请号：US14832021

申请日：2015-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/58 ,  H01L21/288

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20150137375A1

公开(公告)日：2015-05-21

申请号：US14526741

申请日：2014-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen CHEN ,  Jeffrey P. GAMBINO ,  Zhong-Xiang HE ,  Trevor A. THOMPSON ,  Eric J. WHITE

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

公开(公告)号：US20170148672A1

公开(公告)日：2017-05-25

申请号：US15425005

申请日：2017-02-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20160284645A1

公开(公告)日：2016-09-29

申请号：US15178893

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20150364367A1

公开(公告)日：2015-12-17

申请号：US14832024

申请日：2015-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/288

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

Abstract translation: 公开了具有低电阻传导路径的半导体结构和制造方法。 该方法包括在晶片上形成至少一个低电阻传导路径，以及形成与低电阻传导路径直接接触的电镀种子层。

公开(公告)号：US20150137374A1

公开(公告)日：2015-05-21

申请号：US14083929

申请日：2013-11-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen CHEN ,  Jeffrey P. GAMBINO ,  Zhong-Xiang HE ,  Trevor A. THOMPSON ,  Eric J. WHITE

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Abstract translation: 提供了在集成电路中制造铜线的方法。 制造半导体结构的方法包括在掩模中形成线开口。 该方法还包括在导线开口中电镀导电材料。 该方法还包括在导电材料上形成盖层。 该方法还包括去除掩模。 该方法还包括在导电材料的侧面上形成间隔物。 该方法还包括在盖层和侧壁间隔物的表面上形成电介质膜。