公开(公告)号：US20160035621A1

公开(公告)日：2016-02-04

申请号：US14883162

申请日：2015-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen CHEN ,  Jeffrey P. GAMBINO ,  Zhong-Xiang HE ,  Trevor A. THOMPSON ,  Eric J. WHITE

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/288 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

公开(公告)号：US20150332925A1

公开(公告)日：2015-11-19

申请号：US14281166

申请日：2014-05-19

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L21/288 ,  H01L23/532

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20150364416A1

公开(公告)日：2015-12-17

申请号：US14832019

申请日：2015-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20150364368A1

公开(公告)日：2015-12-17

申请号：US14832021

申请日：2015-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/58 ,  H01L21/288

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20150137375A1

公开(公告)日：2015-05-21

申请号：US14526741

申请日：2014-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen CHEN ,  Jeffrey P. GAMBINO ,  Zhong-Xiang HE ,  Trevor A. THOMPSON ,  Eric J. WHITE

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

公开(公告)号：US20150041932A1

公开(公告)日：2015-02-12

申请号：US14515681

申请日：2014-10-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Russell T. HERRIN ,  Christopher V. JAHNES ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: B81B3/00

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.

Abstract translation: 形成至少一个微机电系统（MEMS）空腔的方法包括在布线层和基板上形成第一牺牲腔层。 该方法还包括在第一牺牲腔层上形成绝缘体层。 该方法还包括在绝缘体层上执行反向镶嵌回蚀工艺。 该方法还包括平坦化绝缘体层和第一牺牲腔层。 该方法还包括将第一牺牲腔层排出或剥离到用于MEMS的第一腔的平坦表面。

公开(公告)号：US20170148672A1

公开(公告)日：2017-05-25

申请号：US15425005

申请日：2017-02-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20160284645A1

公开(公告)日：2016-09-29

申请号：US15178893

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

公开(公告)号：US20150364367A1

公开(公告)日：2015-12-17

申请号：US14832024

申请日：2015-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. GAMBINO ,  Thomas J. HARTSWICK ,  Zhong-Xiang HE ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/288

CPC classification number: H01L21/2885 ,  C25D3/38 ,  C25D5/10 ,  C25D7/123 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/585 ,  H01L24/95 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

Abstract translation: 公开了具有低电阻传导路径的半导体结构和制造方法。 该方法包括在晶片上形成至少一个低电阻传导路径，以及形成与低电阻传导路径直接接触的电镀种子层。

公开(公告)号：US20150137374A1

公开(公告)日：2015-05-21

申请号：US14083929

申请日：2013-11-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen CHEN ,  Jeffrey P. GAMBINO ,  Zhong-Xiang HE ,  Trevor A. THOMPSON ,  Eric J. WHITE

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Abstract translation: 提供了在集成电路中制造铜线的方法。 制造半导体结构的方法包括在掩模中形成线开口。 该方法还包括在导线开口中电镀导电材料。 该方法还包括在导电材料上形成盖层。 该方法还包括去除掩模。 该方法还包括在导电材料的侧面上形成间隔物。 该方法还包括在盖层和侧壁间隔物的表面上形成电介质膜。