公开(公告)号：US5864470A

公开(公告)日：1999-01-26

申请号：US883541

申请日：1997-06-25

申请人： Il Kwon Shim ,  Young Wook Heo ,  Robert Francis Darveaux

发明人： Il Kwon Shim ,  Young Wook Heo ,  Robert Francis Darveaux

IPC分类号： H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H01L23/50 ,  H05K7/06

CPC分类号： H01L24/32 ,  H01L23/3677 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181

摘要： A flexible circuit board for a ball grid array semiconductor package including a flexible resin film, a plurality of electrically conductive traces formed on an upper surface of the resin film, the conductive traces having solder ball pads, and a die flag including a semiconductor chip paddle located on a central portion of the circuit board, the chip paddle having a plurality of heat-discharging and grounding solder ball pads, and a plurality of lattice-shaped traces adapted to electrically connect the solder ball pads, the traces being shaped into a lattice to prevent a bleed-out of a silver-filled epoxy resin, a ground bonding rim located around the chip paddle, and a plurality of radial traces adapted to electrically connect the chip paddle to the ground bonding rim, and the flexible resin film being perforated to define solder ball lands on lower surfaces of the solder ball pads. Since the semiconductor chip paddle has an enlarged opened portion, it is possible to minimize the gold plated region, thereby greatly reducing the manufacturing costs. It is also possible to minimize a deformation of the package caused by mechanical stress generated due to a difference in thermal expansion coefficient between different materials of package elements. A bleed-out of silver-filled epoxy resin is also surely prevented.

摘要翻译： 一种用于球栅阵列半导体封装的柔性电路板，包括柔性树脂膜，形成在树脂膜的上表面上的多个导电迹线，具有焊球垫的导电迹线和包括半导体芯片片的裸片标记 位于电路板的中心部分上的芯片焊盘具有多个放热和接地焊球焊盘，以及多个格子状迹线，用于电连接焊球焊盘，所述迹线被成形为格子 以防止银填充的环氧树脂渗漏，位于芯片焊盘周围的接地边缘，以及多个径向迹线，其适于将芯片焊盘电连接到接地边缘，并且柔性树脂膜被穿孔 以限定焊球的下表面上的焊球。 由于半导体芯片焊盘具有扩大的开口部分，因此可以使镀金区域最小化，从而大大降低制造成本。 也可能由于包装元件的不同材料之间的热膨胀系数的差异而产生的机械应力引起的包装变形最小化。 也可以防止银填充环氧树脂渗出。

公开(公告)号：US5953589A

公开(公告)日：1999-09-14

申请号：US915077

申请日：1997-08-20

申请人： Il Kwon Shim ,  Young Wook Heo ,  Robert Francis Darreaux

发明人： Il Kwon Shim ,  Young Wook Heo ,  Robert Francis Darreaux

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/12 ,  H01L23/433 ,  H01L23/498 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/32 ,  H01L21/565 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/73 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A ball grid array semiconductor package using a flexible circuit board, in which the flexible circuit board has no conductive via hole nor solder mask while having a thin structure formed at only one surface thereof with a circuit pattern having a small length. The flexible circuit board is mounted with a metallic carrier frame to achieve an easy handling thereof, a reduction in the inductance, impedance and coupling effect of adjacent circuit patterns and an easy discharge of heat from a semiconductor chip, thereby achieving an improvement in electrical performance and an improvement in heat discharge performance. The metallic carrier frame has a plurality of openings adapted to increase the bonding force between an encapsulate and constituting elements of the package, thereby removing a bending phenomenon of the package, and a method for fabricating such a BGA semiconductor package. The invention also provides a method for fabricating such a BGA semiconductor package.

摘要翻译： 一种使用柔性电路板的球栅阵列半导体封装，其中柔性电路板不具有导电通孔而不具有焊接掩模，同时具有仅在其一个表面上形成具有小长度的电路图案的薄结构。 柔性电路板安装有金属载体框架以实现其易于处理，减小相邻电路图案的电感，阻抗和耦合效应，并且容易地从半导体芯片放电，从而实现电性能的改善 和放热性能的改善。 金属载体框架具有多个开口，其适于增加封装体的封装和构成元件之间的结合力，从而消除封装的弯曲现象，以及制造这种BGA半导体封装的方法。 本发明还提供了制造这种BGA半导体封装的方法。

公开(公告)号：US5729432A

公开(公告)日：1998-03-17

申请号：US588172

申请日：1996-01-18

申请人： Il Kwon Shim ,  Young Wook Heo

发明人： Il Kwon Shim ,  Young Wook Heo

IPC分类号： H01L23/12 ,  H01L23/13 ,  H01L23/31 ,  H01L23/34 ,  H01L23/498 ,  H05K7/20

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/32 ,  H01L2224/29007 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181

摘要： A BGA (ball grid array) semiconductor package with improved heat dissipation and dehumidification effect is disclosed. The above BGA package is provided with an open through slot on the chip mounting portion of the printed circuit board and/or the heat sink. The above through slot is occluded by neither the heat conductive epoxy resin nor the solder mask but is simply opened, thus directly exposing the bottom surface of the semiconductor chip to the outside of the package and effectively performing heat dissipation and dehumidification without causing any pop corn phenomenon during the dehumidification reflow. The size of the open through slot is not larger than the semiconductor chip. The open through slot is selected from among a rectangular slot, a large circular slot, a plurality of small circular slots, a radial slot, a cross slot or any combination thereof.

摘要翻译： 公开了具有改善的散热和除湿效果的BGA（球栅阵列）半导体封装。 上述BGA封装在印刷电路板和/或散热器的芯片安装部分上设置有开放通孔。 上述贯穿槽既不是导热环氧树脂也不是阻焊剂而被简单地打开，因此直接将半导体芯片的底面暴露于封装的外部，并且有效地进行散热和除湿，而不会引起任何流行的玉米 除湿回流期间的现象。 开放槽的尺寸不大于半导体芯片。 开放通槽选自矩形槽，大圆形槽，多个小圆形槽，径向槽，十字槽或其任何组合。

公开(公告)号：US6021563A

公开(公告)日：2000-02-08

申请号：US882687

申请日：1997-06-25

申请人： Young Wook Heo ,  Il Kwon Shim

发明人： Young Wook Heo ,  Il Kwon Shim

IPC分类号： H01L23/28 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L23/544 ,  H01R43/00

CPC分类号： H01L23/3128 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/49121 ,  Y10T29/49155

摘要： A method for marking poor quality printed circuit board units of a printed circuit board strip for ball grid array semiconductor packages wherein at least one degradation-indicating hole is at least partially formed in a poor quality printed circuit board unit of the strip at a region defined between an outer edge of the resin seal molding region of the unit and a cutting line formed on the printed circuit board strip to separate the unit from the strip. Even when a plurality of printed circuit board strips are packed in a vacuum under the condition in which they are stacked, there is no phenomenon that those strips in the pack are permanently deformed, for example, permanently bent. Also, there is no phenomenon that melt resin is leaked from the mold, thereby causing it to be bled out onto the upper surface of the printed circuit board strip. Since no paint is used to mark poor quality printed circuit board units, there is no problem associated with the use of the paint such as a contamination.

摘要翻译： 一种用于标记用于球栅阵列半导体封装的印刷电路板条的质量差的印刷电路板单元的方法，其中至少一个劣化指示孔至少部分地形成在条带的劣质印刷电路板单元中，所述区域被限定在 在单元的树脂密封成型区域的外边缘和形成在印刷电路板条上的切割线之间，以将单元与带分离。 即使在多层印刷电路板条被堆叠在一起的状态下被真空包装的情况下，也不会发生包装中的这些条永久变形的现象，例如永久地弯曲。 此外，没有熔融树脂从模具中泄漏的现象，从而使其被排出到印刷电路板条的上表面上。 由于没有油漆用于标记质量差的印刷电路板单元，所以与使用诸如污染物的涂料没有任何问题。

公开(公告)号：US5854741A

公开(公告)日：1998-12-29

申请号：US651200

申请日：1996-05-17

申请人： Il Kwon Shim ,  Young Wook Heo

发明人： Il Kwon Shim ,  Young Wook Heo

IPC分类号： H01L23/12 ,  H01L23/13 ,  H01L23/14 ,  H01L23/36 ,  H01L23/498 ,  H05K7/20

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/142 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  Y10T29/49121

摘要： A unit printed circuit board (PCB) carrier frame used in the fabrication of a heat sink-attached ball grid array (BGA) semiconductor packages and a method for BGA semiconductor packages using the unit PCB carrier frame. The unit PCB carrier frame has a plurality of die pads each defined at its peripheral edges by elongated slots formed at a strip or reel-shaped frame member. For the fabrication of heat sink-attached BGA semiconductor packages, unit PCBs are bonded to the die pads of the unit PCB carrier frame. Accordingly, the bending of the packages is minimized even when they pass through subsequent processes requiring a high temperature. As a result, it is possible to obtain a maximum number of unit PCBs from a PCB panel, thereby achieving an improvement in productivity.

摘要翻译： 用于制造散热器附着球栅阵列（BGA）半导体封装的单元印刷电路板（PCB）载体框架和使用单元PCB载体框架的BGA半导体封装的方法。 单元PCB载体框架具有多个芯片焊盘，每个芯片焊盘在其周边边缘处由形成在带状或卷状框架构件上的细长槽限定。 为了制造散热器附着的BGA半导体封装，单元PCB被连接到单元PCB载体框架的管芯焊盘。 因此，即使当它们通过需要高温的后续工艺时，封装的弯曲最小化。 结果，可以从PCB面板获得最大数量的单位PCB，从而实现生产率的提高。

公开(公告)号：US5708567A

公开(公告)日：1998-01-13

申请号：US748937

申请日：1996-11-13

申请人： Il Kwon Shim ,  Young Wook Heo

发明人： Il Kwon Shim ,  Young Wook Heo

IPC分类号： H01L23/12 ,  H01L23/04 ,  H01L23/31 ,  H01L23/36 ,  H01L23/367 ,  H01L23/498 ,  H05K7/20

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181

摘要： A BGA (ball grid array) semiconductor package with a ring-type heat sink is disclosed. In the above package, the heat dissipating area is enlarged by extending the edge of a chip mounting die paddle formed of a copper or copper alloy layer to the outside of the package. The ring-type heat sink is attached to the extended portion of the die paddle such that the heat sink surrounds the encapsulant of the package. The above BGA package thus directly and effectively dissipates the chip's heat through the heat sink with high thermal conductivity. A plurality of plated through holes may be formed on the chip mounting portion of the PCB of the above package. The BGA package with both the ring-type heat sink and the PTHs, the heat dissipating effect of the package is further improved.

摘要翻译： 公开了具有环形散热器的BGA（球栅阵列）半导体封装。 在上述封装中，通过将由铜或铜合金层形成的芯片安装片状焊盘的边缘延伸到封装的外部来扩大散热面积。 环形散热器附接到模板的延伸部分，使得散热器围绕封装的密封剂。 因此，上述BGA封装通过散热片直接有效地散发芯片的热量，并具有高导热性。 多个电镀通孔可以形成在上述封装的PCB的芯片安装部分上。 具有环型散热器和PTH的BGA封装，封装的散热效果进一步提高。

公开(公告)号：US07982306B1

公开(公告)日：2011-07-19

申请号：US12799751

申请日：2010-04-30

申请人： Akito Yoshida ,  Young Wook Heo

发明人： Akito Yoshida ,  Young Wook Heo

IPC分类号： H01L23/04 ,  H01L23/12 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

摘要翻译： 可堆叠的半导体封装包括具有包括电路图案的第一侧表面的基板。 每个电路图案包括垫。 半导体管芯电耦合到电路图案。 密封剂在衬垫的内部覆盖半导体管芯和衬底的第一侧表面。 焊料层融合到每个焊盘。 选择直接相邻的焊盘之间的横向距离大于密封剂的侧壁与紧邻的焊盘之间的横向距离，并且焊料层相对于第一侧表面的高度被选择为小于侧壁的高度 使得堆叠在焊料层/焊盘上的半导体封装的未对准是在第二半导体封装中的焊料层和相应的焊球之间并置回流并熔合在一起时进行自校正。

公开(公告)号：US06987314B1

公开(公告)日：2006-01-17

申请号：US10883593

申请日：2004-06-30

申请人： Akito Yoshida ,  Young Wook Heo

发明人： Akito Yoshida ,  Young Wook Heo

IPC分类号： H01L23/04

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

摘要翻译： 可堆叠的半导体封装包括具有包括电路图案的第一侧表面的基板。 每个电路图案包括垫。 半导体管芯电耦合到电路图案。 密封剂在衬垫的内部覆盖半导体管芯和衬底的第一侧表面。 焊料层融合到每个焊盘。 选择直接相邻的焊盘之间的横向距离大于密封剂的侧壁与紧邻的焊盘之间的横向距离，并且焊料层相对于第一侧表面的高度被选择为小于侧壁的高度 使得堆叠在焊料层/焊盘上的半导体封装的未对准是在第二半导体封装中的焊料层和相应焊球的并置的一个被回流熔合在一起时进行自校正。

公开(公告)号：US06879047B1

公开(公告)日：2005-04-12

申请号：US10370013

申请日：2003-02-19

申请人： Young Wook Heo

发明人： Young Wook Heo

IPC分类号： H01L23/31 ,  H01L23/538 ,  H01L23/48

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/03 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor stacking structure and method of producing the same has a flexible substrate. A plurality of apertures is formed on the flexible substrate. The plurality of apertures may be formed in groups for coupling semiconductor devices to the flexible substrate. A plurality of traces is formed on the flexible substrate for coupling the plurality of apertures together. A first semiconductor device is coupled to a first side of the flexible substrate. A first adhesive layer is placed on a first side of the flexible substrate for coupling the first semiconductor device to the first side of the flexible substrate. A plurality of contacts is coupled to a second side of the flexible substrate. The contacts and the first adhesive layer liquefy and flow into designated apertures when heated to couple the contacts to the first semiconductor device.

摘要翻译： 半导体堆叠结构及其制造方法具有柔性基板。 在柔性基板上形成多个孔。 多个孔可以分成多个，以将半导体器件耦合到柔性衬底。 在柔性基板上形成多个迹线，用于将多个孔连接在一起。 第一半导体器件耦合到柔性衬底的第一侧。 第一粘合剂层被放置在柔性基板的第一侧上，用于将第一半导体器件耦合到柔性基板的第一侧。 多个触点耦合到柔性基板的第二侧。 触点和第一粘合剂层在加热时液化并流入指定的孔，以将触点耦合到第一半导体器件。

公开(公告)号：US07459349B1

公开(公告)日：2008-12-02

申请号：US11254339

申请日：2005-10-19

申请人： Akito Yoshida ,  Young Wook Heo

发明人： Akito Yoshida ,  Young Wook Heo

IPC分类号： H01L21/00

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

摘要翻译： 可堆叠的半导体封装包括具有包括电路图案的第一侧表面的基板。 每个电路图案包括垫。 半导体管芯电耦合到电路图案。 密封剂在衬垫的内部覆盖半导体管芯和衬底的第一侧表面。 焊料层融合到每个焊盘。 选择直接相邻的焊盘之间的横向距离大于密封剂的侧壁与紧邻的焊盘之间的横向距离，并且焊料层相对于第一侧表面的高度被选择为小于侧壁的高度 使得堆叠在焊料层/焊盘上的半导体封装的未对准是在第二半导体封装中的焊料层和相应焊球的并置的一个被回流熔合在一起时进行自校正。