公开(公告)号：US20160365258A1

公开(公告)日：2016-12-15

申请号：US14734544

申请日：2015-06-09

Applicant: Infineon Technologies AG

Inventor： Andreas Munding

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83007 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate, a semiconductor chip, and an array of contact elements electrically coupling the substrate to the semiconductor chip. The semiconductor device includes an underfill material between the substrate and the semiconductor chip and between the contact elements. A patterned structure is arranged on the substrate and extends from under the semiconductor chip through a keep-out zone around an edge of the semiconductor chip. The patterned structure provides a reservoir for the underfill material.

Abstract translation: 半导体器件包括衬底，半导体芯片和将衬底电耦合到半导体芯片的接触元件阵列。 半导体器件在衬底和半导体芯片之间以及接触元件之间包括底部填充材料。 图案化结构被布置在基板上并且从半导体芯片下方通过围绕半导体芯片的边缘的保持区延伸。 图案化结构为底部填充材料提供了一个储存器。

公开(公告)号：US10090251B2

公开(公告)日：2018-10-02

申请号：US14808798

申请日：2015-07-24

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Gottfried Beer ,  Juergen Hoegerl ,  Andreas Munding

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/66

Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

公开(公告)号：US20170271298A1

公开(公告)日：2017-09-21

申请号：US15459151

申请日：2017-03-15

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Andreas Munding ,  Catharina Wille

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/09 ,  H01L24/16 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/095 ,  H01L2224/16104 ,  H01L2224/16112 ,  H01L2224/16137 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.

公开(公告)号：US09653671B2

公开(公告)日：2017-05-16

申请号：US14179630

申请日：2014-02-13

Applicant: Infineon Technologies AG

Inventor： Andreas Munding

IPC: H01L29/18 ,  H01L33/64 ,  H01L27/15 ,  H01L33/62 ,  H05B33/08 ,  H01L25/16

CPC classification number: H01L33/644 ,  H01L25/167 ,  H01L27/15 ,  H01L33/62 ,  H01L33/641 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05B33/0821 ,  H01L2924/00014

Abstract: According to various examples, systems, methods, and devices for a light emitting device are described herein. As one example, a light emitting device includes a light emitting element and a capacitor. The capacitor is configured as a voltage buffer for the light emitting element and is further configured to dissipate heat from the light emitting element. According to another example, a carrier for a light emitting arrangement is described herein. According to this example, the carrier includes a capacitor configured to buffer a voltage of the light emitting arrangement. The carrier further includes a contacting structure configured for electrically contacting the light emitting arrangement and the capacitor. The capacitor and the contacting structure are arranged such that the capacitor is configured to dissipate heat from the light emitting arrangement.

公开(公告)号：US10014275B2

公开(公告)日：2018-07-03

申请号：US15459151

申请日：2017-03-15

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Andreas Munding ,  Catharina Wille

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/09 ,  H01L24/16 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/095 ,  H01L2224/16104 ,  H01L2224/16112 ,  H01L2224/16137 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.

公开(公告)号：US20170025357A1

公开(公告)日：2017-01-26

申请号：US14808798

申请日：2015-07-24

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Gottfried Beer ,  Juergen Hoegerl ,  Andreas Munding

IPC: H01L23/538 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L22/32 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14142 ,  H01L2224/14143 ,  H01L2224/16057 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/17051 ,  H01L2224/171 ,  H01L2224/17106 ,  H01L2225/06513 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

Abstract translation: 半导体芯片包括具有有源器件区域的半导体本体，与半导体本体绝缘的一个或多个金属化层，并且被配置为将一个或多个接地，功率和信号传送到有源器件区域，以及多个接触端子形成在 或设置在最外面的一个金属化层上并被配置为提供对半导体芯片的外部电接入。 为半导体芯片定义相邻接触端子之间的最小距离。 接触端子中的一组或多组相邻接触端子具有电气或功能通用性以及小于限定的最小距离的间距。 单个共用焊点可以将半导体芯片的两个或更多个接触端子连接到诸如电路板，插入器或其它半导体芯片的衬底的一个或多个接触端子。

公开(公告)号：US10325783B2

公开(公告)日：2019-06-18

申请号：US14734544

申请日：2015-06-09

Applicant: Infineon Technologies AG

Inventor： Andreas Munding

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, a semiconductor chip, and an array of contact elements electrically coupling the substrate to the semiconductor chip. The semiconductor device includes an underfill material between the substrate and the semiconductor chip and between the contact elements. A patterned structure is arranged on the substrate and extends from under the semiconductor chip through a keep-out zone around an edge of the semiconductor chip. The patterned structure provides a reservoir for the underfill material.