公开(公告)号：US20170012029A1

公开(公告)日：2017-01-12

申请号：US15117708

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： William J. LAMBERT ,  Robert L. SANKMAN ,  Tyler N. OSBORN ,  Charles A. GEALER

IPC: H01L25/11 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L25/117 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5223 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/014

Abstract: An apparatus including a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; and a decoupling capacitor coupled to the TSV's. A method including providing a die including a plurality of through silicon vias (TSV's) extending from a device side to a backside of the die; coupling a decoupling capacitor to the backside of the die. An apparatus including a computing device including a package including a microprocessor including a device side and a backside with through silicon vias (TSV's) extending from the device side to the backside, and a decoupling capacitor coupled to the backside of the die; and a printed circuit board, wherein the package is coupled to the printed circuit board.

Abstract translation: 一种包括模具的设备，所述裸片包括从器件侧延伸到所述管芯的背面的多个穿通硅通孔（TSV）; 以及耦合到TSV的去耦电容器。 一种包括提供包括从所述管芯的器件侧延伸到所述管芯的背面的多个穿通硅通孔（TSV）的管芯的方法; 将去耦电容耦合到芯片的背面。 一种包括计算装置的装置，包括包括微处理器的封装，所述微处理器包括从器件侧延伸到背面的通过硅通孔（TSV）的器件侧和背面;以及耦合到管芯背面的去耦电容器; 以及印刷电路板，其中所述封装件耦合到所述印刷电路板。

公开(公告)号：US20190182958A1

公开(公告)日：2019-06-13

申请号：US16281045

申请日：2019-02-20

Applicant: Intel Corporation

Inventor： Damion SEARLS ,  Weston C. ROTH ,  Margaret D. RAMIREZ ,  James D. JACKSON ,  Rainer E. THOMAS ,  Charles A. GEALER

IPC: H05K1/18 ,  H01L23/498 ,  H01L21/56 ,  H01L25/03

CPC classification number: H05K1/181 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K3/284 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.

公开(公告)号：US20190148275A1

公开(公告)日：2019-05-16

申请号：US16231238

申请日：2018-12-21

Applicant: INTEL CORPORATION

Inventor： Sriram MUTHUKUMAR ,  Charles A. GEALER

IPC: H01L23/498 ,  H01L25/00 ,  H01L23/31 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

公开(公告)号：US20160280539A1

公开(公告)日：2016-09-29

申请号：US15176467

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Qing MA ,  Johanna M. SWAN ,  Min TAO ,  Charles A. GEALER ,  Edward T. ZARBOCK

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81C1/00238 ,  B81C2203/0145 ,  G01P15/0802 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/03 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/01327 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014

Abstract: Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermetically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.

Abstract translation: 传感器芯片与集成电路（IC）芯片的集成。 至少包括第一传感器的第一传感器芯片固定在插入件的第一侧上，以将第一传感器密封在第一空腔内。 IC芯片被固定到与第一传感器相对的插入件的第二侧，IC芯片通过插入器中的通孔电耦合到第一传感器。 在实施例中，第一传感器包括MEMS器件，并且IC芯片包括放大来自MEMS器件的信号的电路。 插入器可以由玻璃制成，其中第一传感器芯片和IC芯片倒装芯片通过压缩或焊接接合到插入器。 横向互连迹线在插入件上的器件和/或其上插入插入物的PCB之间提供I / O。