公开(公告)号：US20210391281A1

公开(公告)日：2021-12-16

申请号：US17412840

申请日：2021-08-26

Applicant: INTEL CORPORATION

Inventor： ERIC J. LI ,  GUOTAO WANG ,  HUIYANG FEI ,  SAIRAM AGRAHARAM ,  OMKAR G. KARHADE ,  NITIN A. DESHPANDE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H05K1/18

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

公开(公告)号：US20190103385A1

公开(公告)日：2019-04-04

申请号：US15721235

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： OMKAR KARHADE ,  ROBERT L. SANKMAN ,  NITIN A. DESHPANDE ,  MITUL MODI ,  THOMAS J. DE BONIS ,  ROBERT M. NICKERSON ,  ZHIMIN WAN ,  HAIFA HARIRI ,  SRI CHAITRA J. CHAVALI ,  NAZMIYE ACIKGOZ AKBAY ,  FADI Y. HAFEZ ,  CHRISTOPHER L. RUMER

IPC: H01L25/10 ,  H01L23/367 ,  H01L23/373 ,  H01L25/00

Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.

公开(公告)号：US20180277492A1

公开(公告)日：2018-09-27

申请号：US15468067

申请日：2017-03-23

Applicant: INTEL CORPORATION

Inventor： ERIC J. LI ,  GUOTAO WANG ,  HUIYANG FEI ,  SAIRAM AGRAHARAM ,  OMKAR G. KARHADE ,  NITIN A. DESHPANDE

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H05K3/30 ,  H05K3/34 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/3511 ,  H05K1/181 ,  H05K3/301 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

公开(公告)号：US20190259713A1

公开(公告)日：2019-08-22

申请号：US16280993

申请日：2019-02-20

Applicant: INTEL CORPORATION

Inventor： ERIC J. LI ,  GUOTAO WANG ,  HUIYANG FEI ,  SAIRAM AGRAHARAM ,  OMKAR G. KARHADE ,  NITIN A. DESHPANDE

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/30 ,  H01L23/31 ,  H05K1/18 ,  H05K3/34

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

公开(公告)号：US20160172323A1

公开(公告)日：2016-06-16

申请号：US14571623

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： YOSHIHIRO TOMITA ,  JIRO KUBOTA ,  OMKAR G. KARHADE ,  SHAWNA M. LIFF ,  KINYA ICHIKAWA ,  NITIN A. DESHPANDE

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/18 ,  H01L21/566 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.

Abstract translation: 微电子封装可以形成有围绕微电子管芯的图框加强件，以减少微电子封装的翘曲。 用于制造这种微电子封装的实施例可以包括形成具有有源表面和相对背面的微电子管芯，其中微电子管芯有源表面可以附接到微电子衬底。 可以形成具有穿过其中的开口的相框加强件并将其放置在脱模膜上，其中模塑材料可以沉积在画框加强件和释放膜上。 微电子管芯可以插入模具材料中，其中微电子管芯的至少一部分延伸到相框开口中。 可以去除剥离膜，然后可以移除在微电子管芯背表面上延伸的一部分模具材料以形成微电子封装。