公开(公告)号：US20240170430A1

公开(公告)日：2024-05-23

申请号：US18515364

申请日：2023-11-21

申请人： X Display Company Technology Limited

发明人： Carl Prevatte ,  Christopher Bower ,  Ronald S. Cok ,  Matthew Meitl

IPC分类号： H01L23/00 ,  H01L21/48 ,  H05K1/11 ,  H05K3/30 ,  H05K3/34

CPC分类号： H01L24/11 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H05K1/112 ,  H05K3/3436 ,  H01L21/4803 ,  H01L21/4846 ,  H01L2224/1144 ,  H01L2224/11466 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/1418 ,  H01L2224/16227 ,  H01L2224/1624 ,  H01L2224/17107 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044 ,  H01L2924/1304 ,  H05K3/305 ,  H05K2201/09409 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10143

摘要： A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.

公开(公告)号：US20180211895A1

公开(公告)日：2018-07-26

申请号：US15923412

申请日：2018-03-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： TIEN-CHUNG YANG ,  LIN-CHIH HUANG ,  HSIEN-WEI CHEN ,  AN-JHIH SU ,  LI-HSIEN HUANG

IPC分类号： H01L23/31 ,  H01L23/482 ,  H01L23/485 ,  H01L23/00 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L23/3114 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/94 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0391 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/11013 ,  H01L2224/11466 ,  H01L2224/11602 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/03

摘要： A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric material over the semiconductor substrate and surrounding the conductor, and a seed layer between the polymeric material and the conductor. A top surface of the conductor, a top surface of the polymeric material and a top surface of the seed layer are substantially coplanar.

公开(公告)号：US09929069B2

公开(公告)日：2018-03-27

申请号：US15380499

申请日：2016-12-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Tien-Chung Yang ,  Lin-Chih Huang ,  Hsien-Wei Chen ,  An-Jhih Su ,  Li-Hsien Huang

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L23/482 ,  H01L23/485 ,  H01L23/00 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L23/3114 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/94 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0391 ,  H01L2224/04105 ,  H01L2224/10126 ,  H01L2224/11013 ,  H01L2224/11466 ,  H01L2224/11602 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/03

摘要： A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a polymeric material over the semiconductor substrate and the conductive pad; patterning the polymeric material to form an opening exposing at least a portion of the conductive pad; disposing a conductive layer over the polymeric material and the portion of the conductive pad; and forming a conductor over the portion of the conductive pad and within the opening.

公开(公告)号：US09355952B2

公开(公告)日：2016-05-31

申请号：US14798395

申请日：2015-07-13

申请人： Intel Corporation

发明人： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L21/44 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/50 ,  H05K1/11 ,  H05K3/10 ,  H05K3/42 ,  H01L21/56 ,  H05K3/34

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

公开(公告)号：US08963326B2

公开(公告)日：2015-02-24

申请号：US13312730

申请日：2011-12-06

申请人： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

发明人： Xusheng Bao ,  Ma Phoo Pwint Hlaing ,  Jian Zuo

IPC分类号： H01L23/498

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/035 ,  H01L2224/03505 ,  H01L2224/0361 ,  H01L2224/03632 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05086 ,  H01L2224/05088 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11466 ,  H01L2224/118 ,  H01L2224/11849 ,  H01L2224/11916 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13078 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/01013 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00013 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

摘要翻译： 半导体器件具有在半导体晶片的表面上形成有第一导电层的半导体晶片。 在半导体晶片和第一导电层的表面上形成第一绝缘层。 在第一绝缘层和第一导电层上形成第二导电层。 在第一绝缘层和第二导电层上形成第二绝缘层。 在半导体晶片的凸块形成区域中的第二绝缘层中形成多个开口以暴露第二导电层并减少电迁移的不利影响。 开口由第二绝缘层的一部分分开。 UBM层形成在电连接到第二导电层的凸块形成区域中的第二绝缘层的开口上方。 在UBM层上形成凸点。

公开(公告)号：US11990438B2

公开(公告)日：2024-05-21

申请号：US17984748

申请日：2022-11-10

申请人： X Display Company Technology Limited

发明人： Carl Prevatte ,  Christopher Bower ,  Ronald S. Cok ,  Matthew Meitl

IPC分类号： H01L23/00 ,  H01L21/48 ,  H05K1/11 ,  H05K3/30 ,  H05K3/34

CPC分类号： H01L24/11 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H05K1/112 ,  H05K3/3436 ,  H01L21/4803 ,  H01L21/4846 ,  H01L2224/1144 ,  H01L2224/11466 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/1418 ,  H01L2224/16227 ,  H01L2224/1624 ,  H01L2224/17107 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044 ,  H01L2924/1304 ,  H05K3/305 ,  H05K2201/09409 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10143 ,  H01L2924/12041 ,  H01L2924/00012 ,  H01L2924/12044 ,  H01L2924/00012 ,  H01L2924/12043 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012

摘要： A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.

公开(公告)号：US20240113066A1

公开(公告)日：2024-04-04

申请号：US18264719

申请日：2022-01-28

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： Takashi IMAHIGASHI

IPC分类号： H01L23/00 ,  H01S5/0234 ,  H01S5/026

CPC分类号： H01L24/73 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01S5/0234 ,  H01S5/0261 ,  H01L24/11 ,  H01L24/27 ,  H01L2224/05073 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1145 ,  H01L2224/11466 ,  H01L2224/1147 ,  H01L2224/11848 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13169 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/2745 ,  H01L2224/27466 ,  H01L2224/2747 ,  H01L2224/27848 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29169 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2924/01203 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12042 ,  H01L2924/1426

摘要： An electronic device according to the present disclosure includes a semiconductor substrate, a chip, a bump, and a sidewall portion. The bump connects a plurality of connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip. The sidewall portion includes a porous metal layer and that annularly surrounds a region where a plurality of bumps is provided, and connects the semiconductor substrate and the chip. The chip has a thermal expansion coefficient different from that of the semiconductor substrate by 0.1 ppm/° C. or more. The chip is a semiconductor laser, and the semiconductor substrate includes a drive circuit that drives the semiconductor laser.

公开(公告)号：US09761550B2

公开(公告)日：2017-09-12

申请号：US15098116

申请日：2016-04-13

申请人： Infineon Technologies Americas Corp.

发明人： Robert Montgomery ,  Hugo Burke ,  Phillip Parsonage ,  Susan Johns ,  David Paul Jones

IPC分类号： H01L23/00 ,  H01L29/66 ,  H01L29/78 ,  H01L21/56 ,  H01L29/417

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L29/41775 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/11019 ,  H01L2224/11466 ,  H01L2224/11831 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05494 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

公开(公告)号：US08835217B2

公开(公告)日：2014-09-16

申请号：US12975934

申请日：2010-12-22

申请人： Mark S Hlad ,  Islam A Salama ,  Mihir K Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

发明人： Mark S Hlad ,  Islam A Salama ,  Mihir K Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC分类号： H01L21/44 ,  H01L23/02

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

摘要翻译： 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

公开(公告)号：US08791525B2

公开(公告)日：2014-07-29

申请号：US12036718

申请日：2008-02-25

申请人： Robert Montgomery ,  Hugo Burke ,  Philip Parsonage ,  Susan Johns ,  David Paul Jones

发明人： Robert Montgomery ,  Hugo Burke ,  Philip Parsonage ,  Susan Johns ,  David Paul Jones

IPC分类号： H01L29/76

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L29/41775 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/11019 ,  H01L2224/11466 ,  H01L2224/11831 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05494 ,  H01L2924/13091 ,  H01L2924/00

摘要： A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

摘要翻译： 一种功率半导体器件及其制造方法，其包括在其有源区上的薄金属层和厚金属层的堆叠。