公开(公告)号：US20160155667A1

公开(公告)日：2016-06-02

申请号：US15018686

申请日：2016-02-08

Applicant: INTEL CORPORATION

Inventor： Aleksandar ALEKSOV ,  Tony DAMBRAUSKAS ,  Danish FARUQUI ,  Mark S. HLAD ,  Edward R. PRACK

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00 ,  H01L21/027

CPC classification number: H01L24/11 ,  H01L21/02118 ,  H01L21/02263 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/3205 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76883 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3142 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81026 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81375 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81913 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.

Abstract translation: 描述了电子组件及其制造。 一个实施例涉及一种方法，包括在半导体晶片上的金属凸块上沉积有机薄膜层，该有机薄膜层也形成在与晶片上的金属凸块相邻的表面上。 将晶片切割成多个半导体管芯结构，该管芯结构包括有机薄膜层。 半导体管芯结构附着到基板上，其中，附接包括在管芯结构上的金属凸块和衬底上的焊盘之间形成焊料接合，并且其中焊料接合延伸穿过有机薄膜层。 然后将有机薄膜层暴露于等离子体。 描述和要求保护其他实施例。

公开(公告)号：US20150318238A1

公开(公告)日：2015-11-05

申请号：US14798395

申请日：2015-07-13

Applicant: Intel Corporation

Inventor： Mark S. HLAD ,  Islam A. SALAMA ,  Mihir K. ROY ,  Tao WU ,  Yueli LIU ,  Kyu Oh LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract translation: 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

公开(公告)号：US20170141061A1

公开(公告)日：2017-05-18

申请号：US15421340

申请日：2017-01-31

Applicant: INTEL CORPORATION

Inventor： Aleksandar ALEKSOV ,  Tony DAMBRAUSKAS ,  Danish FARUQUI ,  Mark S. HLAD ,  Edward R. PRACK

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/683 ,  H01L21/311 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L21/027

CPC classification number: H01L24/11 ,  H01L21/02118 ,  H01L21/02263 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/3205 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76883 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3142 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81026 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81375 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81913 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.