公开(公告)号：US09355952B2

公开(公告)日：2016-05-31

申请号：US14798395

申请日：2015-07-13

申请人： Intel Corporation

发明人： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L21/44 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/50 ,  H05K1/11 ,  H05K3/10 ,  H05K3/42 ,  H01L21/56 ,  H05K3/34

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

公开(公告)号：US08962471B2

公开(公告)日：2015-02-24

申请号：US13912826

申请日：2013-06-07

申请人： Toshinori Ogashiwa ,  Masayuki Miyairi

发明人： Toshinori Ogashiwa ,  Masayuki Miyairi

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11416 ,  H01L2224/11442 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11505 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/75251 ,  H01L2224/75343 ,  H01L2224/81097 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/8121 ,  H01L2224/81444 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/01203 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/384 ,  H01L2924/20103 ,  H01L2924/20107 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.

摘要翻译： 一种双层结构凸块，其包括形成在基板上的第一导电金属的本体的第一凸起层，其为金，铜和镍中的任一个，所述第一凸起层形成在基板上的粉末的烧结体的第二凸起层 第二导电金属，其是形成在第一凸块层上的任何金和银。 通过电镀，溅射或CVD中的任何一种形成构成第一凸块层的体本体。 构成第二凸点层的烧结体通过烧结纯度为99.9重量％以上且平均粒径为0.005μm〜1.0μm的第二导电性金属的粉末而形成。 第二凸点层的杨氏模量为第一凸点层的杨氏模量的0.1〜0.4倍。

公开(公告)号：US20120161330A1

公开(公告)日：2012-06-28

申请号：US12975934

申请日：2010-12-22

申请人： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

发明人： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/52

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

摘要翻译： 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

公开(公告)号：US20160074971A1

公开(公告)日：2016-03-17

申请号：US14785179

申请日：2013-04-18

申请人： SENJU METAL INDUSTRY CO., LTD.

发明人： Ken Tachibana ,  Hikaru Nomura

IPC分类号： B23K35/26 ,  C22C12/00 ,  H01L23/00 ,  C22C13/02

CPC分类号： B23K35/262 ,  B23K1/0016 ,  B23K35/264 ,  C22C12/00 ,  C22C13/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/01109 ,  H01L2924/01322 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15701 ,  H05K3/3463 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/00014 ,  H01L2924/00

摘要： Disclosed is a Sn—Bi—Cu—Ni series lead-free solder alloy which has a low melting point, good ductility and high tensile strength, suppresses strain in the substrate by suppressing generation of P-rich layer on a joining interface to have high shear strength and is superior in joining reliability. In order to suppress diffusion of Cu and Ni in an electrode and to maintain elongation and wettability of the solder alloy, a solder alloy has an alloy composition containing 31 to 59 mass % of Bi, 0.3 to 1.0 mass % of Cu, 0.01 to 0.06 mass % of Ni and balance of Sn.

摘要翻译： 公开了一种Sn-Bi-Cu-Ni系无铅焊料合金，它具有低熔点，良好的延展性和高拉伸强度，通过抑制在接合界面上产生富P层从而抑制基板中的应变，使其具有高 剪切强度，连接可靠性优异。 为了抑制电极中Cu和Ni的扩散，并且为了保持焊料合金的伸长率和润湿性，焊料合金具有合金组成，其含有Bi为31〜59质量％，Cu为0.3〜1.0质量％，0.01〜0.06 Ni的质量％和Sn的平衡。

公开(公告)号：US20150318238A1

公开(公告)日：2015-11-05

申请号：US14798395

申请日：2015-07-13

申请人： Intel Corporation

发明人： Mark S. HLAD ,  Islam A. SALAMA ,  Mihir K. ROY ,  Tao WU ,  Yueli LIU ,  Kyu Oh LEE

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

摘要翻译： 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

公开(公告)号：US20110272802A1

公开(公告)日：2011-11-10

申请号：US13144411

申请日：2010-03-05

申请人： Toshinori Ogashiwa ,  Masayuki Miyairi

发明人： Toshinori Ogashiwa ,  Masayuki Miyairi

IPC分类号： H01L23/498 ,  H01L21/28

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11416 ,  H01L2224/11442 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11505 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/75251 ,  H01L2224/75343 ,  H01L2224/81097 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/8121 ,  H01L2224/81444 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/01203 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/384 ,  H01L2924/20103 ,  H01L2924/20107 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.

摘要翻译： 一种双层结构凸块，其包括形成在基板上的第一导电金属的本体的第一凸起层，其为金，铜和镍中的任一个，所述第一凸起层形成在基板上的粉末的烧结体的第二凸起层 第二导电金属，其是形成在第一凸块层上的任何金和银。 通过电镀，溅射或CVD中的任何一种形成构成第一凸块层的体本体。 构成第二凸点层的烧结体通过烧结纯度为99.9重量％以上且平均粒径为0.005μm〜1.0μm的第二导电性金属的粉末而形成。 第二凸点层的杨氏模量为第一凸点层的杨氏模量的0.1〜0.4倍。

公开(公告)号：US20150200178A1

公开(公告)日：2015-07-16

申请号：US14153755

申请日：2014-01-13

申请人： Infineon Technologies Austria AG

发明人： Ralf Otremba ,  Josef Höglauer ,  Jürgen Schredl ,  Xaver Schlögel ,  Klaus Schiess

IPC分类号： H01L23/00 ,  H01L23/556

CPC分类号： H01L24/29 ,  H01L23/552 ,  H01L23/556 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/29083 ,  H01L2224/29116 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01103 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.

摘要翻译： 提供了一种连接结构，其包括半导体衬底，布置在半导体衬底上的第一层，第一层被配置为提供屏蔽防放射线，第二层布置在第一层上，第二层包括包含Pb的焊料，以及 布置在第二层上的导电构件。

公开(公告)号：US20140295619A1

公开(公告)日：2014-10-02

申请号：US13912826

申请日：2013-06-07

申请人： TOSHINORI OGASHIWA ,  MASAYUKI MIYAIRI

发明人： TOSHINORI OGASHIWA ,  MASAYUKI MIYAIRI

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11416 ,  H01L2224/11442 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11505 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/75251 ,  H01L2224/75343 ,  H01L2224/81097 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/8121 ,  H01L2224/81444 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/01203 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/384 ,  H01L2924/20103 ,  H01L2924/20107 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.

摘要翻译： 一种双层结构凸块，其包括形成在基板上的第一导电金属的本体的第一凸起层，其为金，铜和镍中的任一个，所述第一凸起层形成在基板上的粉末的烧结体的第二凸起层 第二导电金属，其是形成在第一凸块层上的任何金和银。 通过电镀，溅射或CVD中的任何一种形成构成第一凸块层的体本体。 构成第二凸点层的烧结体通过烧结纯度为99.9重量％以上且平均粒径为0.005μm〜1.0μm的第二导电性金属的粉末而形成。 第二凸点层的杨氏模量为第一凸点层的杨氏模量的0.1〜0.4倍。

公开(公告)号：US08835217B2

公开(公告)日：2014-09-16

申请号：US12975934

申请日：2010-12-22

申请人： Mark S Hlad ,  Islam A Salama ,  Mihir K Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

发明人： Mark S Hlad ,  Islam A Salama ,  Mihir K Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC分类号： H01L21/44 ,  H01L23/02

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

摘要翻译： 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

公开(公告)号：US08492894B2

公开(公告)日：2013-07-23

申请号：US13144411

申请日：2010-03-05

申请人： Toshinori Ogashiwa ,  Masayuki Miyairi

发明人： Toshinori Ogashiwa ,  Masayuki Miyairi

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11416 ,  H01L2224/11442 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11505 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/75251 ,  H01L2224/75343 ,  H01L2224/81097 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/8121 ,  H01L2224/81444 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/01203 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/384 ,  H01L2924/20103 ,  H01L2924/20107 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.

摘要翻译： 一种双层结构凸块，其包括形成在基板上的第一导电金属的本体的第一凸起层，其为金，铜和镍中的任一个，所述第一凸起层形成在基板上的粉末的烧结体的第二凸起层 第二导电金属，其是形成在第一凸块层上的任何金和银。 通过电镀，溅射或CVD中的任何一种形成构成第一凸块层的体本体。 构成第二凸点层的烧结体通过烧结纯度为99.9重量％以上，平均粒径为0.005μm〜1.0μm的第二导电性金属的粉末而形成。 第二凸点层的杨氏模量为第一凸点层的杨氏模量的0.1〜0.4倍。