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    NANOWIRE STRESS SENSORS AND STRESS SENSOR INTEGRATED CIRCUITS, DESIGN STRUCTURES FOR A STRESS SENSOR INTEGRATED CIRCUIT, AND RELATED METHODS
    2.
    发明申请
    NANOWIRE STRESS SENSORS AND STRESS SENSOR INTEGRATED CIRCUITS, DESIGN STRUCTURES FOR A STRESS SENSOR INTEGRATED CIRCUIT, AND RELATED METHODS 有权
    纳米应力传感器和应力传感器集成电路，应力传感器集成电路的设计结构及相关方法

    公开(公告)号：US20130145857A1

    公开(公告)日：2013-06-13

    申请号：US13764169

    申请日：2013-02-11

    申请人： International Business Machines Corporation

    发明人： Andres Bryant ,  Oki Gunawan ,  Shih-Hsien Lo ,  Jeffrey W. Sleight

    IPC分类号： H01L29/66 ,  G01B7/16

    CPC分类号： H01L29/66477 ,  B82Y10/00 ,  B82Y40/00 ,  G01B7/16 ,  G01B7/18 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/66439 ,  H01L29/775 ,  Y10S977/724 ,  Y10S977/938 ,  Y10S977/956

    摘要： Methods for sensing a mechanical stress and methods of making stress sensor integrated circuits. The sensing methods include transferring the mechanical stress from the object to one or more nanowires in a stress sensor or stress sensor circuit and permitting the nanowires to change in length in response to the mechanical stress. An electrical characteristic of the stress sensor or stress sensor circuit, which has a variation correlated with changes in the magnitude of the mechanical stress, is measured and then assessed to determine the stress magnitude. The manufacture methods include electrically connecting nanowire field effect transistors having, as channel regions, one or more nanowires of either a different crystalline orientation or a different body width for the individual nanowires so that an offset output voltage results when mechanical strain is applied to the nanowires.

    摘要翻译： 用于感应机械应力的方法和制造应力传感器集成电路的方法。 感测方法包括将机械应力从物体转移到应力传感器或应力传感器电路中的一个或多个纳米线，并允许纳米线响应于机械应力而改变长度。 测量应力传感器或应力传感器电路的电特性，其具有与机械应力幅度的变化相关的变化，然后评估以确定应力幅度。 制造方法包括电连接纳米线场效应晶体管，其具有作为沟道区的单个纳米线的不同晶体取向或不同体宽的一个或多个纳米线，使得当对纳米线施加机械应变时产生偏移输出电压 。

    METHOD FOR QUADRUPLE FREQUENCY FINFETS WITH SINGLE-FIN REMOVAL
    3.
    发明申请
    METHOD FOR QUADRUPLE FREQUENCY FINFETS WITH SINGLE-FIN REMOVAL 有权
    具有单金属去除功能的四元频率FinFET方法

    公开(公告)号：US20160225634A1

    公开(公告)日：2016-08-04

    申请号：US14613416

    申请日：2015-02-04

    申请人： International Business Machines Corporation

    发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    IPC分类号： H01L21/308 ,  H01L29/66 ,  H01L21/311 ,  H01L21/027 ,  H01L21/306 ,  H01L21/8234

    CPC分类号： H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211

    摘要： A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch. A second double density pattern of second sidewall spacers is produced on a layer disposed above the first double density pattern from second mandrels formed by a second mask with a the minimum pitch that is shifted relative to the first mask. A single sidewall spacer is removed from either the first or second double density pattern of first and second sidewall spacers. Sidewall image transfer processes allow the formation of quadruple density fins from which but a single fin is removed.

    摘要翻译： 用于四重密度翅片的单翅片去除的方法。 第一侧壁间隔物的第一双重密度图案在半导体衬底上由使用最小间距的第一掩模形成的第一心轴产生。 在由第二掩模形成的第二芯轴上设置有第二双重密度图案上方的第二侧壁间隔物的第二双重密度图案具有相对于第一掩模移动的最小间距。 从第一和第二侧壁间隔物的第一或第二双重密度图案中去除单个侧壁间隔物。 侧壁图像转印过程允许形成四重密度翅片，但是除去单个翅片。

    ZRAM heterochannel memory
    4.
    发明授权
    ZRAM heterochannel memory 有权
    ZRAM异或通道存储器

    公开(公告)号：US09105707B2

    公开(公告)日：2015-08-11

    申请号：US13949609

    申请日：2013-07-24

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Andres Bryant ,  Lyndon R. Logan ,  Edward J. Nowak ,  Robert R. Robison

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L27/108

    CPC分类号： H01L29/78 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/7841

    摘要： Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.

    摘要翻译： 提供零电容存储单元的方法。 制造半导体结构的方法包括通过掺杂第一种杂质的第一材料形成沟道区。 该方法包括通过用不同于第一种类型杂质的第二类型杂质掺杂第二材料来形成源极/漏极区域，其中第二材料具有比第一材料更小的带隙。 该方法包括在沟道区域和源极/漏极区域之间形成轻掺杂区域，其中轻掺杂区域包括第二材料。 该方法包括在通道区域上形成栅极，其中第二材料在栅极的边缘延伸。

    METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET
    5.
    发明申请
    METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET 有权
    用于形成和结构的用于大量生长的源/排水带的方法

    公开(公告)号：US20130122668A1

    公开(公告)日：2013-05-16

    申请号：US13687240

    申请日：2012-11-28

    申请人： International Business Machines Corporation

    发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Jed H. Rankin

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

    摘要： A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer. Each of the fins has a central semiconductor portion and conductive end portions. At least one conductive strap is positioned within the insulator layer below the fins. The conductive strap can be perpendicular to the fins and contact the fins. The conductive strap includes recessed portions disposed within the insulator layer, below the plurality of fins, and between each of the plurality of fins, and projected portions disposed above the insulator layer, collinear with each of the plurality of fins. The conductive strap is disposed in at least one of a source region and a drain region of the semiconductor structure. A gate insulator contacts and covers the central semiconductor portion of the fins, and a gate conductor covers and contacts the gate insulator.

    摘要翻译： 一种方法和半导体结构包括在衬底上的绝缘体层，在绝缘体层之上的多个平行鳍片。 每个翅片具有中心半导体部分和导电端部。 至少一个导电带位于鳍片下方的绝缘体层内。 导电带可以垂直于翅片并接触翅片。 导电带包括设置在绝缘体层内的凹陷部分，多个散热片下方以及多个翅片中的每一个之间的凹陷部分，以及设置在绝缘体层上方的突出部分，与多个翅片中的每一个共线。 导电带设置在半导体结构的源极区域和漏极区域中的至少一个中。 栅极绝缘体接触并覆盖翅片的中心半导体部分，并且栅极导体覆盖并接触栅极绝缘体。

    Bulk finFET well contacts with fin pattern uniformity
    8.
    发明授权
    Bulk finFET well contacts with fin pattern uniformity 有权
    散装finFET阱接触鳍片图案均匀

    公开(公告)号：US09240352B2

    公开(公告)日：2016-01-19

    申请号：US13659292

    申请日：2012-10-24

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Scott R. Stiffler

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823821 ,  H01L27/0924

    摘要： Bulk finFET well contacts with fin pattern uniformity and methods of manufacture. The method includes providing a substrate with a first region and a second region, the first region comprising a well with a first conductivity. The method further includes forming contiguous fins over the first region and the second region. The method further includes forming an epitaxial layer on at least one portion of the fins in the first region and at least one portion of the fins in the second region. The method further includes doping the epitaxial layer in the first region with a first type dopant to provide the first conductivity. The method further includes doping the epitaxial layer in the second region with a second type dopant to provide a second conductivity.

    摘要翻译： 散装finFET良好的接触鳍片图案均匀性和制造方法。 该方法包括提供具有第一区域和第二区域的衬底，所述第一区域包括具有第一导电性的阱。 该方法还包括在第一区域和第二区域上形成连续的翅片。 该方法还包括在第一区域中的翅片的至少一部分上形成外延层，以及在第二区域中形成翅片的至少一部分。 该方法还包括在第一区域中用第一类型掺杂剂掺杂外延层以提供第一导电性。 该方法还包括在第二区域中用第二种掺杂剂掺杂外延层以提供第二导电性。

    STRUCTURE AND METHOD TO FORM A FINFET DEVICE
    9.
    发明申请
    STRUCTURE AND METHOD TO FORM A FINFET DEVICE 有权
    构造FINFET器件的结构和方法

    公开(公告)号：US20150303272A1

    公开(公告)日：2015-10-22

    申请号：US14576611

    申请日：2014-12-19

    申请人： International Business Machines Corporation

    发明人： Andres Bryant ,  Jeffrey B. Johnson ,  Effendi Leobandung ,  Tenko Yamashita

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    摘要： A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.

    摘要翻译： 一种制造FinFET器件的方法包括：形成具有覆盖掩埋氧化物（BOX）层的半导体层的绝缘体上硅（SOI）衬底; 蚀刻半导体层以在多个翅片结构和BOX层之间形成多个翅片结构和半导体层间隙; 在至少一个栅极区上沉积牺牲栅极，其中栅极区域分离源区和漏区; 在牺牲栅极的垂直侧壁上设置偏置间隔物; 去除牺牲门; 去除所述栅极区域中的半导体层间隙，以防止所述栅极区域中的所述多个翅片结构的合流; 以及制造覆盖栅极区域中的鳍结构的高k电介质金属栅极结构。