公开(公告)号：US06687870B1

公开(公告)日：2004-02-03

申请号：US09406173

申请日：1999-09-23

申请人： Jafar Mohseni ,  Brian Butler ,  Deepu John ,  Haitao Zhang

发明人： Jafar Mohseni ,  Brian Butler ,  Deepu John ,  Haitao Zhang

IPC分类号： H03M1300

CPC分类号： H03M13/2792 ,  H03M13/2707 ,  H03M13/276 ,  H03M13/2782

摘要： Interleavers are used in data transmission and storage applications to introduce diversity into a data stream, thereby making adjacent symbols more independent with respect to a transfer environment of variable quality. Conventional interleavers require storage in whole units of data blocks. This storage requirement complicates implementations for applications where available circuit area is limited and data rates and block sizes are large. A novel interleaver produces an interleaved data block using storage space that is only a fraction of the size of the input data block.

摘要翻译： 交织器用于数据传输和存储应用中以将分集引入到数据流中，从而使相邻符号相对于可变质量的传送环境更独立。 传统的交织器需要在整个数据块中存储。 这种存储要求使可用电路面积有限并且数据速率和块大小较大的应用的实现复杂化。 一种新颖的交织器使用只是输入数据块大小的一小部分的存储空间产生交错数据块。

公开(公告)号：US06535562B1

公开(公告)日：2003-03-18

申请号：US09452045

申请日：1999-11-30

申请人： Mohammad Jafar Mohseni ,  Brian Butler ,  Deepu John ,  Haitao Zhang

发明人： Mohammad Jafar Mohseni ,  Brian Butler ,  Deepu John ,  Haitao Zhang

IPC分类号： H04L2736

CPC分类号： H04L27/206 ,  H04L27/2082

摘要： In applications employing phase-shift keying modulation, a phase rotator as disclosed herein is used to rotate the constellation of signal vectors before carrier modulation in order to maximize modulator output power. Such a rotator may be applied in the digital domain (to complex signals having either binary-valued or multi-valued components) or in the analog domain.

摘要翻译： 在采用相移键控调制的应用中，如本文所公开的相位旋转器用于在载波调制之前旋转信号矢量的星座，以便最大化调制器输出功率。 这种旋转器可以应用于数字域（具有二进制值或多值分量的复信号）或模拟域中。

公开(公告)号：US07046701B2

公开(公告)日：2006-05-16

申请号：US09973249

申请日：2001-10-09

申请人： Mohammad J. Mohseni ,  Brian K. Butler ,  Deepu John ,  Haitao Zhang

发明人： Mohammad J. Mohseni ,  Brian K. Butler ,  Deepu John ,  Haitao Zhang

IPC分类号： H04J3/02

CPC分类号： H04J3/047 ,  H04L7/0008 ,  H04L7/0029 ,  H04L7/02

摘要： A composite signal has two components, each carrying a stream of information that may be digital. In one application of a method according to an embodiment of the invention, at least one of the components is delayed such that a time relation between the streams of information is altered. The components are transferred via a common signal path such that upon transfer, the original time relation between the streams of information may be restored.

公开(公告)号：US06999500B2

公开(公告)日：2006-02-14

申请号：US10005453

申请日：2001-11-02

申请人： Mohammad J. Mohseni ,  Brian K. Butler ,  Deepu John ,  Haitao Zhang

发明人： Mohammad J. Mohseni ,  Brian K. Butler ,  Deepu John ,  Haitao Zhang

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H04B1/7093 ,  H04B1/707

摘要： A spreading system according to an embodiment of the invention spreads two data signals. The system produces a filtered signal that is based on one of the data signals and an output signal that is based on both of the data signals. In one example, a spreading system is used to perform QPSK spreading of two data signals, including separate processing of the two data signals, in a practical manner. Such separate control may include filtering and/or gain control.

公开(公告)号：US06820103B2

公开(公告)日：2004-11-16

申请号：US10003913

申请日：2001-10-31

申请人： Brian K. Butler ,  Deepu John ,  Haitao Zhang ,  Mohammad J. Mohseni

发明人： Brian K. Butler ,  Deepu John ,  Haitao Zhang ,  Mohammad J. Mohseni

IPC分类号： G06F1710

CPC分类号： H03H17/0657 ,  H03H17/0226 ,  H03H17/0238 ,  H03H17/06 ,  H03H17/0607

摘要： A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.

摘要翻译： 用于数字滤波的系统包括一组逻辑门，状态存储器和多路复用器。 状态存储器包括两个或多个存储体，并且还可以包括组合逻辑和/或至少一个查找表。 在一个应用中，根据有限脉冲响应滤波器系数向量进行滤波操作，而不进行运行时乘法。 对对称和反对称滤波器系数向量的应用进行了描述，以及用于滤除任意奇数或偶数长度的系数向量的应用。

公开(公告)号：US06615341B2

公开(公告)日：2003-09-02

申请号：US09876189

申请日：2001-06-05

申请人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

发明人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

IPC分类号： G06F9302

CPC分类号： G06F9/3816 ,  G06F9/30014 ,  G06F9/30098 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/3885 ,  G06F15/7857

摘要： A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

公开(公告)号：US06425070B1

公开(公告)日：2002-07-23

申请号：US09044086

申请日：1998-03-18

申请人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee

发明人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee

IPC分类号： G06F9302

CPC分类号： G06F9/3816 ,  G06F9/30014 ,  G06F9/30098 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/3885 ,  G06F15/7857

摘要： The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.

摘要翻译： 本发明是用于数字信号处理的新颖且改进的方法和电路。 本发明的一个方面要求使用可变长度指令集。 可变长度指令的一部分可以存储在存储器空间内的相邻位置，同时跨越存储器字边界的指令的开始和结束。 此外，通过使指令包含可变数量的指令片段来实现本发明的附加方面。 每个指令片段导致执行特定操作或操作，允许在每个时钟周期期间进行多个操作。 因此，在每个时钟周期期间执行多个操作，减少执行任务所需的总时钟周期数。 示例性DSP包括一组三个数据总线，数据可以通过该数据总线与寄存器组和三个数据存储器交换。 使用两条以上的数据总线，特别是三条数据总线，实现了本发明的另一方面，这显着减少了总线竞争。 本发明的一个实施例要求数据总线包括一个宽的总线和两个窄的总线。 宽总线耦合到宽数据存储器，并且两个窄总线耦合到两个窄数据存储器。 通过使用具有可由至少两个处理单元访问的寄存器的寄存器组来实现本发明的另一方面。 这允许通过多个处理单元对特定数据集执行多个操作，而不向存储器读取和写入数据。 本发明的示例性实施例中的处理单元包括算术逻辑（ALU）和乘法累加（MAC）单元。 当结合使用多总线架构，高度并行指令或两者时，实现本发明的另一方面，其中执行高度流水线化，多操作的处理。

公开(公告)号：US20050208959A1

公开(公告)日：2005-09-22

申请号：US10889926

申请日：2004-07-12

申请人： Tao Chen ,  Baaziz Achour ,  Brian Butler ,  Edward Tiedemann ,  Haitao Zhang ,  Keith Saints ,  Luca Blessent ,  Yongbin Wei

发明人： Tao Chen ,  Baaziz Achour ,  Brian Butler ,  Edward Tiedemann ,  Haitao Zhang ,  Keith Saints ,  Luca Blessent ,  Yongbin Wei

IPC分类号： H04W72/14 ,  H04B7/005 ,  H04L12/18 ,  H04W4/06 ,  H04W52/08 ,  H04W52/32 ,  H04W52/54 ,  H04Q7/20

CPC分类号： H04W4/06 ,  H04L12/189 ,  H04W52/08 ,  H04W52/322 ,  H04W52/327 ,  H04W52/54 ,  H04W72/005

摘要： A dynamic shared forward link channel (or “data” channel) is used to send multicast data to a group of wireless devices, e.g., using a common long code mask for the data channel. Reference power control (PC) bits are also sent on the data channel and used for signal quality estimation. A shared forward link control channel is used to send user-specific signaling to individual wireless devices, e.g., using time division multiplexing (TDM) and a unique long code mask for each wireless device. A shared forward link indicator channel is used to send reverse link (RL) PC bits to the wireless devices, e.g., using TDM. The data channel is jointly power controlled by all wireless devices receiving the data channel. The control and indicator channels are individually power controlled by each wireless device such that the signaling and RL PC bits sent on these channels for the wireless device are reliably received.

摘要翻译： 使用动态共享前向链路信道（或“数据”信道）将组播数据发送到一组无线设备，例如使用用于数据信道的公共长码掩码。 参考功率控制（PC）位也在数据通道上发送并用于信号质量估计。 共享的前向链路控制信道用于向各个无线设备发送用户特定的信令，例如对于每个无线设备使用时分多路复用（TDM）和唯一的长码掩码。 共享的前向链路指示符信道用于向无线设备发送反向链路（RL）PC比特，例如使用TDM。 数据通道由接收数据通道的所有无线设备共同供电控制。 控制和指示器通道由每个无线设备单独进行功率控制，使得在这些信道上为无线设备发送的信令和RL PC位被可靠地接收。

公开(公告)号：US09968915B2

公开(公告)日：2018-05-15

申请号：US14404774

申请日：2012-07-27

申请人： Xionghou Gao ,  Haitao Zhang ,  Di Li ,  Xueli Li ,  Hongchang Duan ,  Zhengguo Tan ,  Chaowei Liu ,  Yunfeng Zheng ,  Xiaoliang Huang ,  Jinjun Cai ,  Chenxi Zhang ,  Zhishuang Pan ,  Gengzhen Cao

发明人： Xionghou Gao ,  Haitao Zhang ,  Di Li ,  Xueli Li ,  Hongchang Duan ,  Zhengguo Tan ,  Chaowei Liu ,  Yunfeng Zheng ,  Xiaoliang Huang ,  Jinjun Cai ,  Chenxi Zhang ,  Zhishuang Pan ,  Gengzhen Cao

IPC分类号： B01J29/06 ,  B01J29/08 ,  B01J29/80 ,  B01J37/30 ,  B01J35/10 ,  C01B39/02 ,  B01J37/28 ,  C01B39/24 ,  C01B39/54 ,  B01J37/00 ,  B01J37/04 ,  B01J37/06 ,  B01J37/08

CPC分类号： B01J29/088 ,  B01J29/084 ,  B01J29/80 ,  B01J35/10 ,  B01J35/109 ,  B01J37/009 ,  B01J37/04 ,  B01J37/06 ,  B01J37/08 ,  B01J37/28 ,  B01J37/30 ,  B01J2229/18 ,  B01J2229/186 ,  B01J2229/40 ,  B01J2229/42 ,  C01B39/026 ,  C01B39/24 ,  C01B39/54

摘要： Provided is a phosphorus-containing ultrastable Y-type rare earth (RE) molecular sieve and the preparation method thereof. The method is: based on NaY molecular sieve as a raw material, obtaining “one-exchange one-roast” RE-Na Y-type molecular sieve through the steps of exchanging with RE, pre-exchanging with dispersing, and the first calcination; and then performing ammonium salt exchange, phosphorus modification, and the second calcination on the “one-exchange one-roast” RE-Na Y-type molecular sieve, wherein the sequence of the RE exchange and the pre-exchange with dispersing is unlimited, and the sequence of the ammonium salt exchange and the phosphorus modification is unlimited as well. The obtained molecular sieve contains RE oxide 1-20 wt %, phosphorus 0.1-5 wt %, and sodium oxide no more than 1.2 wt %, and has a crystallization degree of 51-69% and a lattice parameter of 2.449-2.469 nm. Heavy oil conversion rate can be increased by using the molecular sieve as an active component in a catalytic cracking catalyst.

公开(公告)号：US09844772B2

公开(公告)日：2017-12-19

申请号：US14364536

申请日：2012-04-13

申请人： Xionghou Gao ,  Haitao Zhang ,  Zhengguo Tan ,  Di Li ,  Dong Ji ,  Hongchang Duan ,  Chenxi Zhang

发明人： Xionghou Gao ,  Haitao Zhang ,  Zhengguo Tan ,  Di Li ,  Dong Ji ,  Hongchang Duan ,  Chenxi Zhang

IPC分类号： B01J29/06 ,  B01J29/80 ,  C01B39/24 ,  C01B39/02 ,  B01J35/10 ,  B01J35/08 ,  B01J37/00 ,  B01J37/30 ,  B01J29/08 ,  B01J29/40 ,  B01J35/00 ,  B01J35/02

CPC分类号： B01J29/80 ,  B01J29/088 ,  B01J29/40 ,  B01J35/002 ,  B01J35/023 ,  B01J35/08 ,  B01J35/10 ,  B01J35/1085 ,  B01J35/109 ,  B01J37/0018 ,  B01J37/0045 ,  B01J37/30 ,  B01J2029/062 ,  B01J2229/186 ,  B01J2229/37 ,  B01J2229/40 ,  B01J2229/42 ,  C01B39/026 ,  C01B39/24

摘要： The present invention relates to a heavy oil catalytic cracking catalyst and preparation method thereof. The catalyst comprises 2 to 50% by weight of an ultra-stable rare earth type Y molecular sieve, 0.5 to 30% by weight of one or more other molecular sieves, 0.5 to 70% by weight of clay, 1.0 to 65% by weight of high-temperature-resistant inorganic oxides, and 0.01 to 12.5% by weight of rare earth oxide. The ultra-stable rare earth type Y molecular sieve is obtained as follows: the raw material, NaY molecular sieve, is subjected to a rare earth exchange and a dispersing pre-exchange, and the molecular sieve slurry is filtered, washed and subjected to a first calcination to produce a “one-exchange one-calcination” rare earth sodium Y molecular sieve, wherein the order of the rare earth exchange and the dispersing pre-exchange is not limited; and the “one-exchange one-calcination” rare earth sodium Y molecular sieve is further subjected to ammonium salt exchange for sodium reduction and a second calcination. The catalyst provided in the present invention is characteristic in its high heavy-oil-conversion capacity, a high total liquid yield and a high light oil yield.