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公开(公告)号：US20140027700A1
公开(公告)日：2014-01-30
申请号：US13562063
申请日：2012-07-30
CPC分类号： H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column.
摘要翻译： 制造具有嵌入式切换层的忆阻器的方法包括将通孔内的第一电极材料的表面部分暴露于反应性物质，以形成嵌入通孔内和表面的开关层。 通孔与第一导体迹线接触。 该方法还包括沉积与通孔表面相邻的第二电极材料层，并将该层图案化成与通孔对准的列。 该方法还包括沉积层间绝缘材料以围绕该柱并提供与该柱的第二电极材料电接触的第二导体迹线。
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公开(公告)号：US08658463B2
公开(公告)日：2014-02-25
申请号：US13562063
申请日：2012-07-30
IPC分类号： H01L21/00 , H01L21/16 , H01L21/20 , H01L47/00 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column.
摘要翻译： 制造具有嵌入式切换层的忆阻器的方法包括将通孔内的第一电极材料的表面部分暴露于反应性物质，以形成嵌入通孔内和表面的开关层。 通孔与第一导体迹线接触。 该方法还包括沉积与通孔表面相邻的第二电极材料层，并将该层图案化成与通孔对齐的列。 该方法还包括沉积层间绝缘材料以围绕该柱并提供与该柱的第二电极材料电接触的第二导体迹线。
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公开(公告)号：US20230184922A1
公开(公告)日：2023-06-15
申请号：US18165882
申请日：2023-02-07
申请人： Janice H. Nickel
发明人： Janice H. Nickel
CPC分类号： G01S13/758 , E01F9/30 , E01F9/578 , E01F9/553
摘要： An apparatus includes a pavement marker configured to be mounted to a road at a lane line of a lane at known orientation with respect to the lane line; and an RF device carried by the raised pavement marker. The RF device is configured to transmit a directional RF navigation signal and it is positioned relative to the known orientation to transmit the signal across the lane in a direction that is substantially normal to the lane line.
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公开(公告)号：US09299746B2
公开(公告)日：2016-03-29
申请号：US14345295
申请日：2011-10-12
CPC分类号： H01L27/2463 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2213/33 , G11C2213/72 , H01L29/88 , H01L45/16
摘要： The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a backward diode disposed in series with the memory element between the memory element and either the first conductor or the second conductor.
摘要翻译： 本公开提供了一种存储单元，其包括设置在第一导体和第二导体之间的电阻性存储元件，第一导体和第二导体被配置为激活电阻式存储元件。 存储单元还包括与存储元件串联设置在存储元件与第一导体或第二导体之间的后向二极管。
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公开(公告)号：US20150076438A1
公开(公告)日：2015-03-19
申请号：US14396406
申请日：2012-07-31
申请人： Hans S. Cho , Janice H. Nickel , R. Stanley Williams , Jaesung Roh , Jinwon Park , Choi Hyejung , Moonsig Joo , Jiwon Moon , Changgoo Lee , Yongsun Sohn , Jeongtae Kim
发明人： Hans S. Cho , Janice H. Nickel , R. Stanley Williams , Jaesung Roh , Jinwon Park , Choi Hyejung , Moonsig Joo , Jiwon Moon , Changgoo Lee , Yongsun Sohn , Jeongtae Kim
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , H01L27/101 , H01L27/2463 , H01L45/08 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/1641 , H01L45/1675 , H01L45/1691
摘要： Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion.
摘要翻译： 本公开的实例包括非易失性电阻存储器单元及其形成方法。 非易失性电阻性存储单元的示例包括在第一电极上形成为垂直延伸结构的非易失性电阻性存储单元的第一部分，其中第一部分包括跨越垂直宽度的至少一个阻聚材料 延伸结构。 非易失性电阻性存储单元还包括在第一部分的至少一个侧壁上形成为垂直延伸的忆阻材料结构的第二部分。
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公开(公告)号：US08314475B2
公开(公告)日：2012-11-20
申请号：US12942131
申请日：2010-11-09
IPC分类号： H01L29/93
摘要： One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between the first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. Additional examples of the present invention include integrated circuits that contain multiple nanoscale electronic devices that each includes an anisotropic dielectric material layered between first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material.
摘要翻译： 本发明的一个实例是纳米级电子器件，其包括第一导电电极，第二导电电极和各向异性介电材料，其分层在第一和第二电极之间，其电介质的方向大致在第一和第二电极之间的最短距离的方向上 在各向异性介电材料内的第二电极小于其它方向的介电常数。 本发明的另外的实例包括集成电路，其包含多个纳米尺度的电子器件，每个电子器件包括分层在第一和第二电极之间的各向异性介电材料，其电介质的方向大致在第一和第二电极之间的最短距离之间的介电常数小于介电常数 在各向异性介电材料内的其它方向。
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公开(公告)号：US07397098B2
公开(公告)日：2008-07-08
申请号：US10733089
申请日：2003-12-11
IPC分类号： G11C11/14
CPC分类号： G11C11/1675 , G11C11/161
摘要： An aspect of the present invention is an MRAM device. The MRAM device includes a plurality of magnetic memory elements, a sense line coupled to the plurality of magnetic memory elements for sensing a magnetic orientation of each of the plurality of magnetic memory elements wherein the sense line includes a first via and a second via and wherein the sense line is utilized to thermally assist in switching a magnetic orientation of at least one of the plurality of magnetic memory elements.
摘要翻译： 本发明的一个方面是MRAM装置。 MRAM装置包括多个磁存储器元件，感测线耦合到多个磁存储元件，用于感测多个磁存储元件中的每一个的磁取向，其中感测线包括第一通孔和第二通孔，并且其中 感测线被用于热辅助切换多个磁存储元件中的至少一个的磁取向。
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公开(公告)号：US20080083744A1
公开(公告)日：2008-04-10
申请号：US11469588
申请日：2006-09-01
IPC分类号： H05B3/08
CPC分类号： H05B3/265 , H05B3/267 , H05B2203/003
摘要： A microheater for heating at least one target area, the microheater comprising a substrate, a resistive material adjacent to the substrate and connector traces connected to the resistive material. The microheater is formed so that when a predetermined current flows through the resistive material, the target area is heated to a substantially isothermal temperature.
摘要翻译： 用于加热至少一个目标区域的微加热器，所述微加热器包括基板，邻近所述基板的电阻材料和连接到所述电阻材料的连接器迹线。 微加热器形成为使得当预定电流流过电阻材料时，目标区域被加热到基本上等温的温度。
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公开(公告)号：US07339817B2
公开(公告)日：2008-03-04
申请号：US10315748
申请日：2002-12-10
申请人： Janice H. Nickel , Lung T. Tran
发明人： Janice H. Nickel , Lung T. Tran
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/1675
摘要： A magnetic memory element is written to by heating the memory element and applying at least one magnetic field to the memory element.
摘要翻译： 通过加热存储元件并将至少一个磁场施加到存储元件来写入磁存储元件。
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10.发明授权Magnetoresistive device including pinned structure with a layer that provides texture for pinning 有权磁阻器件包括具有提供钉扎纹理的层的钉扎结构公开(公告)号：US06989975B2
公开(公告)日：2006-01-24
申请号：US10463993
申请日：2003-06-18
申请人： Janice H. Nickel , Manish Sharma
发明人： Janice H. Nickel , Manish Sharma
IPC分类号： G11B5/39
CPC分类号： B82Y25/00 , B82Y10/00 , G11B5/012 , G11B5/3903 , G11B5/3909 , G11B2005/3996 , G11C11/15 , H01F10/3254 , H01F10/3268 , H01F10/3295 , H01L43/08
摘要： A magnetoresistive device includes a free ferromagnetic layer; a pinned structure; and a spacer layer between the free layer and the pinned structure. The pinned structure may include first, second and third ferromagnetic layers that are ferromagnetically coupled. The first and third layers are separated by the second layer. The second layer has a lower magnetic moment than the first and third layers. In the alternative, the pinned structure may include a single layer of Co50Fe50.
摘要翻译： 磁阻器件包括自由铁磁层; 固定结构 以及在自由层和钉扎结构之间的间隔层。 钉扎结构可以包括铁磁耦合的第一，第二和第三铁磁层。 第一和第三层由第二层隔开。 第二层具有比第一层和第三层更低的磁矩。 在替代方案中，钉扎结构可以包括单层Co 50 N 50 O 50。
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